IP Library Granted Patent US 8,119,431
Granted Patent B2
US 8,119,431 · App. 12/632,940 · Granted Feb 21, 2012

Method of forming a micro-electromechanical system (MEMS) having a gap stop

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Quick Facts
Patent No.
US 8,119,431
App. No.
12/632,940
Granted
Feb 21, 2012
Kind
B2
Abstract

A method of forming a micro-electromechanical system (MEMS) includes providing a cap substrate, providing a support substrate, depositing a conductive material over the support substrate, patterning the conductive material to form a gap stop and a contact, wherein the gap stop is separated form the contact by an opening, forming a bonding material over the contact and in the opening, wherein the gap stop and the contact prevent the bonding material from extending outside the opening, and attaching the cap substrate to the support substrate by the step of forming the bonding material. In addition, the structure is described.

Claims (46)

1. A method of forming a micro-electromechanical system (MEMS) comprising:

providing a cap substrate;

providing a support substrate;

depositing a conductive material over the support substrate;

patterning the conductive material to leave a conductive portion that forms a gap stop and a contact, wherein the gap stop is separated form the contact by an opening;

forming a bonding material over the contact and in the opening, wherein the gap stop and the contact prevent the bonding material from extending outside the opening; and

attaching the cap substrate to the support substrate by the step of forming the bonding material;

wherein forming the bonding material comprises:

forming a semiconductor layer over the conductive material; and

heating the cap substrate and the semiconductor layer to form the bonding material and bond the cap substrate to the support substrate; and

further comprising forming a stack over the conductive material wherein the step of forming the semiconductor layer is part of the step of forming the stack;

wherein the step of forming the stack over the conductive portion further comprises:

forming a seed layer comprising silicon over the conductive portion; and

forming a first layer comprising silicon and germanium over the seed layer; and

wherein the step of forming the semiconductor layer further comprises forming a second layer comprising germanium over the first layer.

2. The method of claim 1 , further comprising:

patterning the stack before the step of patterning the conductive material.

3. The method of claim 2 , further comprising:

forming an oxide prior to forming the conductive material;

patterning the oxide before the step of forming the stack over the conductive material; and

removing the oxide after the step of patterning the conductive material.

4. The method of claim 2 , wherein providing the cap substrate further comprises providing a cap substrate having an aluminum layer formed in contact with one surface of the cap substrate and wherein after the step of forming the bonding material, the aluminum layer is in contact with the bonding material.

5. The method of claim 4 , wherein the bonding material comprises a eutectic material comprising aluminum and germanium.

6. The method of claim 1 , wherein the step of depositing the conductive material further comprises depositing doped polysilicon.

7. The method of claim 1 , wherein the step of attaching the cap substrate to the support substrate further comprises forming a capacitor in an area of the cap substrate and the support substrate.

8. A method of forming a micro-electromechanical system (MEMS) comprising

providing a first structure, wherein the first structure comprises a cap wafer and a first conductive material formed on an edge of the cap wafer;

providing a second structure, wherein the step of providing the second structure comprises:

providing a support wafer;

depositing a second conductive material over the support wafer;

patterning the second conductive material to form an opening in the second conductive material, a gap stop, and a contact, wherein the opening is between the gap stop and the contact; and

forming a semiconductor stack over the contact; and

bonding the first structure to the second structure by heating the semiconductor layer so it flows into the opening and the gap stop and the contact stop the semiconductor layer from flowing outside of the opening;

wherein the step of heating the semiconductor layer comprises heating the semiconductor stack to form a eutectic bonding material; and

wherein the step of forming the semiconductor stack comprises:

forming a seed layer comprising silicon over the second conductive material;

forming a first semiconductor layer over the seed layer, wherein the first semiconductor layer comprises silicon and germanium; and

forming a second semiconductor layer over the first semiconductor layer, wherein the second semiconductor layer comprises germanium; and

wherein the step of heating the semiconductor stack to form the eutectic bonding material comprises forming an aluminum and germanium comprising eutectic bonding material.

9. The method of claim 8 , further comprising patterning the stack before the step of patterning the second conductive material.

10. The method of claim 9 , further comprising:

forming an oxide prior to forming the second conductive material;

patterning the oxide before the step of forming the semiconductor stack; and

removing the oxide after the step of patterning the second conductive material.

11. The method of claim 8 , wherein the step of depositing the second conductive material further comprises depositing doped polysilicon.

12. The method of claim 8 , wherein after the step of bonding the first structure to the second structure, the first structure and the second conductive material are separated from each other by a dimension that is approximately equal to a height of the gap stop.

Assignments (15)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037355/0723 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 024079/0082 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2009
From: PARK, WOO TAE; KARLIN, LISA H.; LIU, LIANJUN
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 023621/0932 →