Flash memory device with a plurality of source plates
View Patent ↗A flash memory device and a method of manufacturing a flash memory device. A flash memory device may include an isolation layer and/or an active area over a semiconductor substrate, a memory gate formed over an active area, a control gate formed over a semiconductor substrate including a memory gate, and/or a common source line contact formed over a semiconductor substrate including a control gate. A flash memory device may include a source plate having substantially the same interval as an interval of an active area of a bit line. A source plate may include an active area in which a common source line contact may be formed. A common source line contact may include a long butting contact extending in a direction traversing an active area.
1. An apparatus comprising
an isolation layer and plurality of active areas over a semiconductor substrate, wherein the plurality of active areas are spaced apart from each other in a regular interval distance;
at least one of a memory gate, a control gate and a common source line contact over said semiconductor substrate; and
a plurality of source plates, wherein said plurality of source plates are spaced apart from each other in the regular interval distance that is substantially the same interval distance as the regular interval distance of plurality of active areas of a bit line.
2. The apparatus of claim 1 , wherein said source plate comprises an active area over which a common source line contact is formed.
3. The apparatus of claim 2 , wherein said common source line contact comprises a long butting contact extending in a direction traversing said active area of said source plate.
4. The apparatus of claim 3 , wherein said long butting contact connects at least two active areas of said source plate.
5. The apparatus of claim 3 , wherein said long butting contact is connected with adjacent expansion areas.
6. The apparatus of claim 2 , comprising an expansion area over said active area of said source plate.
7. The apparatus of claim 6 , wherein said expansion area and said isolation layer are simultaneously formed.
8. The apparatus of claim 2 , comprising a plurality of expansion areas over said source plate over which said common source line contact is formed.
9. The apparatus of claim 1 , comprising a flash memory device.
10. The apparatus of claim 1 , wherein said memory gate comprises at least one of:
a stack gate type; and
a silicon-oxide-nitride-oxide-silicon structure.