Semiconductor device and manufacturing method thereof for reducing the area of the memory cell region
View Patent ↗A structure is adopted for a layout of an SRAM cell which provides a local wiring 3 a between a gate 2 a and gate 2 b and connects an active region 1 a and an active region 1 b . This eliminates the necessity for providing a contact between the gate 2 a and the gate 2 b . Therefore, it is possible to reduce the size of a memory cell region C in a short side direction. Furthermore, a structure whereby a left end of a gate 2 c is retreated from the gate 2 a and a local wiring 3 b which connects the active region 1 b and gate 2 c disposed in a diagonal direction is adopted. This allows the gate 2 a to be shifted toward the center of the memory cell region C.
1. A method of manufacturing a semiconductor device, comprising the steps of:
(a) preparing a substrate;
(b) forming a first active region in the substrate and forming a second active region, which is separated from the first active region, in the substrate;
(c) forming a first gate electrode region which is crossed by the first active region, and separated from the second active region, and forming a second gate electrode region which is crossed by the first active region and the second active region, and separated from the first gate electrode region, and forming a third gate electrode region which is separated from the first active region, the first gate electrode region and the second gate electrode region;
(d) after step (a) to (c), forming an insulating film, which is separated from a top of the first gate electrode region, a top of the second gate electrode region and a top of the third gate electrode region, over the substrate;
(e) after step (d), etching the insulating film and the third gate electrode region so as to form a groove on the third gate electrode region, on the first active region, on the second active region and over a region between the first active region and the second active region;
(f) after step (a) to (e), forming a conductive film over the substrate; and
(g) after step (f), removing the conductive film out of the groove, reaching the top of the first gate electrode region, the top of the second gate electrode region and the top of the third gate electrode region and forming a wiring which connects the first active region, the second active region and the third gate electrode region.
2. A method of manufacturing a semiconductor device according to claim 1 , wherein the first active region and the second active region are extended in the first direction, and the first gate electrode region, the second gate electrode region and the third gate electrode region are extended in the second direction which is different direction from the first direction.
3. A method of manufacturing a semiconductor device according to claim 2 , wherein the first active region, the second active region, the first gate electrode region, second gate electrode region and the third gate electrode region are formed in a memory cell in the substrate, a center of the memory cell region is extended in the first direction, the first active region is formed next to the second active region, and the second active region is closer to the center of the memory cell than the first active region.
4. A method of manufacturing a semiconductor device according to claim 3 , wherein the second gate electrode region and the third gate electrode region are crossed by the center of the memory cell region, and the first gate electrode region is separated from the center of the memory cell.
5. A method of manufacturing a semiconductor device according to claim 4 , wherein the first direction and the second direction orthogonally cross.