Light emitting device having light extraction structure and method for manufacturing the same
View Patent ↗A nitride-based light emitting device capable of achieving an enhancement in emission efficiency and an enhancement in reliability is disclosed. The light emitting device includes a semiconductor layer, and a light extracting layer arranged on the semiconductor layer and made of a material having a refractive index equal to or higher than a reflective index of the semiconductor layer.
1. A method for manufacturing a light emitting device, comprising:
growing a semiconductor structure having multi-layers over a substrate;
forming a first electrode over a first surface of the semiconductor structure;
providing a support layer on the first electrode;
removing the substrate from a second surface of the semiconductor structure;
forming a dielectric layer over the second surface of the semiconductor structure;
forming a plurality of holes in the dielectric layer;
forming a plurality of grooves in the semiconductor structure by using the dielectric layer as a mask, the grooves forming a rough surface through which light is extracted or a photonic crystal structure;
removing the dielectric layer; and
forming a second electrode over the second surface of the semiconductor structure.
2. The method according to claim 1 , wherein growing the semiconductor structure comprises:
forming a first-type semiconductor layer over the substrate;
forming an active layer over the first-type semiconductor layer; and
forming a second-type semiconductor layer over the active layer.
3. The method according to claim 2 , wherein the first-type is n-type and the second-type is p-type.
4. The method according to claim 2 , wherein the grooves are formed with a depth corresponding to ⅓ or more of a thickness of the first-type semiconductor layer.
5. The method according to claim 1 , wherein the dielectric layer comprises an oxide or a nitride.
6. The method according to claim 1 , wherein the holes or the grooves are formed with a regular pattern.
7. The method according to claim 6 , wherein the regular pattern comprises one of a square pattern, an oblique-line pattern, a concentric pattern, a polygonal pattern, a trapezoidal pattern, or a radial pattern.
8. The method according to claim 1 , wherein forming the plurality of holes or forming the plurality of grooves is carried out by using a dry etching process.
9. The method according to claim 8 , wherein the dry etching process is a reactive ion etching (RIE) process or an inductively-coupled plasma reactive ion etching (ICP-RIE) process.
10. The method according to claim 8 , wherein the dry etching process is performed by using at least one of Ar, BCl 3 , Cl 2 , CF 4 , and CHF 3 .
11. The method according to claim 1 , wherein forming the plurality of holes in the dielectric layer is performed by forming the holes in a region where the second electrode is not to be formed.
12. The method according to claim 11 , wherein the second electrode is formed on the region.
13. The method according to claim 1 , wherein the grooves are configured to enhance light extraction efficiency of the light emitting device.
14. The method according to claim 1 , wherein each photonic crystal structure has a periodicity of 0.5 to 1.5 μm.
15. The method according to claim 14 , wherein the groove has a diameter corresponding to about 0.3 to 0.6 times of the periodicity.
16. The method according to claim 1 , wherein the first electrode comprises a reflective electrode.
17. The method according to claim 1 , wherein forming the plurality of holes is carried out by using a pattern mask on the dielectric layer.
18. The method according to claim 17 , wherein the pattern mask comprises a metal or a photoresist.
19. The method according to claim 1 , wherein the second surface is a main light emitting surface of the light emitting device.
20. The method according to claim 1 , wherein the grooves are irregularly distributed to form the rough surface.
21. The method according to claim 1 , wherein providing the support layer comprises bonding a semiconductor substrate.
22. The method according to claim 21 , wherein the semiconductor substrate comprises silicon, gallium arsenide, or germanium.
23. The method according to claim 1 , wherein providing the support layer comprises plating a metal.
24. The method according to claim 23 , wherein the metal comprises nickel or copper.
25. The method according to claim 1 , further comprising forming a seed metal on the first electrode.
26. The method according to claim 1 , wherein removing the substrate is performed by a laser lift-off process or an etching process.
27. The method according to claim 1 , wherein the semiconductor structure comprises a GaN-based semiconductor.