Formation of high-K gate stacks in semiconductor devices
View Patent ↗A method of forming a high-K gate stack for a MOSFET device to control the threshold voltage for the MOSFET device. A first high-K metallic oxide layer is formed on a semiconductor substrate. At least one composite layer is then formed directly on the first layer. The composite layer is composed of a second high-K metallic oxide layer formed directly on a dipole induction layer. The dipole induction layer includes a high-K metallic oxide having higher oxygen vacancy affinity and lower oxygen vacancy diffusivity than the first and second layers. A metallic gate electrode is then formed on the composite layer. Formation of the various layers is such as to position the dipole induction layer of the composite layer between the gate electrode and substrate so as to shift the threshold voltage to a desired level. A high-K gate stack in a MOSFET device formed by the above method is also provided.
1. A method for forming a high-K gate stack for a MOSFET device to control the threshold voltage for the MOSFET device, the method comprising:
forming a first layer of high-K metallic oxide on a semiconductor substrate, the first layer having a barrier layer sandwiched between portions of the high-K metallic oxide of the first layer;
forming at least one composite layer directly on said first layer, said composite layer including a second layer of high-K metallic oxide formed directly on a dipole induction layer, the dipole induction layer comprising a high-K metallic oxide having higher oxygen vacancy affinity and lower oxygen vacancy diffusivity than said first and second layers; and
forming a metallic gate electrode on said at least one composite layer;
wherein formation of said layers is such as to position the dipole induction layer of said at least one composite layer between the gate electrode and substrate to shift said threshold voltage to a desired level.
2. The method according to claim 1 wherein the dipole induction layer contains at least one of lanthanum and yttrium.
3. The method according to claim 2 wherein the dipole induction layer comprises at least one of La2O3, LayHfzOx, LayHfzSiOx, Y2O3 and LaYzHfwSiOx.
4. The method according to claim 1 wherein a single composite layer is formed on the first layer.
5. The method according to claim 4 wherein the dipole induction layer has a thickness of from 5 Å to 20 Å, contains lanthanum with an average concentration of from 30% to 100%, and is spaced at from 5 Å to 20 Å from one of the gate electrode and substrate.
6. The method according to claim 5 wherein formation of said layers is such as to position the dipole induction layer one of nearer to the gate electrode than to the substrate or nearer to the substrate than to the gate electrode.
7. The method according to claim 4 wherein the dipole induction layer has a thickness of from 5 Å to 20 Å, contains lanthanum with an average concentration of from 30% to 100%, and is spaced from 2.5 Å to 5 Å from one of the gate electrode and substrate.
8. The method according to claim 7 wherein formation of said layers is such as to position the dipole induction layer one of nearer to the gate electrode than to the substrate or nearer to the substrate than to the gate electrode.
9. The method according to claim 1 wherein the gate electrode is formed directly on said composite layer.
10. The method according to claim 1 wherein said first and second layers comprise at least one of HfO2 and HfxOSi.
11. The method according to claim 10 wherein the first and second layers are formed such that the concentration of Hf increases in a direction away from the substrate.
12. The method according to claim 1 wherein the barrier layer comprises a high-K metallic oxide having higher oxygen vacancy affinity and lower oxygen vacancy diffusivity than the portions, whereby the barrier layer inhibits migration of oxygen vacancies across the barrier layer towards the substrate.
13. The method according to claim 12 wherein the barrier layer contains at least one of lanthanum and yttrium.
14. The method according to claim 13 wherein the barrier layer comprises at least one of La2O3, LaxHfyOx, LaxHfySiOx, Y2O3, and LaxTyHfzSiOx.
15. The method according to claim 14 wherein the barrier layer contains lanthanum with an average concentration of at least 80% and has a thickness of from 2.5 Å to 5 Å.
16. The method according to claim 12 wherein the barrier layer is positioned substantially midway between the gate electrode and substrate.
17. A high-K gate in a MOSFET device formed by the method of claim 1 .