IP Library Granted Patent US 8,138,062
Granted Patent B2
US 8,138,062 · App. 12/638,424 · Granted Mar 20, 2012

Electrical coupling of wafer structures

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Quick Facts
Patent No.
US 8,138,062
App. No.
12/638,424
Granted
Mar 20, 2012
Kind
B2
Abstract

A method for electrically coupling a first wafer with a second wafer is provided. The method includes bonding the first wafer with the second wafer using a bonding material. The method further includes forming an opening in the first wafer in a scribe area of the second wafer to expose a surface of a conductive structure of the second wafer. The method further includes forming a conductive layer overlying the first wafer and the opening in the first wafer such that the conductive layer forms an electrical contact with the conductive structure of the second wafer thereby electrically coupling the first wafer with the second wafer.

Claims (39)

1. A method for electrically coupling a first wafer with a second wafer, the method comprising:

bonding the first wafer with the second wafer;

forming an opening in the first wafer in a scribe area of the second wafer to expose a surface of a conductive structure of the second wafer; and

forming a conductive layer overlying the first wafer and the opening in the first wafer such that the conductive layer forms an electrical contact with the conductive structure of the second wafer thereby electrically coupling the first wafer with the second wafer,

wherein the bonding the first wafer with the second wafer includes bonding the first wafer with the second wafer using a bonding material, wherein the forming the opening includes forming an opening in the bonding material.

2. The method of claim 1 , wherein forming the opening through the first wafer comprises sawing through the first wafer in the scribe area of the second wafer.

3. The method of claim 1 , wherein the second wafer comprises at least one micro-electro-mechanical systems (MEMS) device.

4. The method of claim 1 further comprising sawing through the second wafer to separate the bonded first and second wafers into a plurality of die, wherein the sawing includes sawing through a saw path in the scribe area.

5. A method for electrically coupling a first wafer with a second wafer, the method comprising:

bonding the first wafer with the second wafer;

forming an opening in the first wafer in a scribe area of the second wafer to expose a surface of a conductive structure of the second wafer; and

forming a conductive layer overlying the first wafer and the opening in the first wafer such that the conductive layer forms an electrical contact with the conductive structure of the second wafer thereby electrically coupling the first wafer with the second wafer,

wherein the second wafer comprises a plurality of pads and the method further comprising forming a second opening in the first wafer to expose the plurality of pads, after the forming the opening in the first wafer.

6. The method of claim 5 , wherein the bonding the first wafer with the second wafer includes bonding the first wafer with the second wafer using a bonding material, wherein the forming the opening includes forming an opening in the bonding material.

7. A method for electrically coupling a first wafer with a second wafer, the method comprising:

bonding the first wafer with the second wafer;

forming an opening in the first wafer in a scribe area of the second wafer to expose a surface of a conductive structure of the second wafer;

forming a conductive layer overlying the first wafer and the opening in the first wafer such that the conductive layer forms an electrical contact with the conductive structure of the second wafer thereby electrically coupling the first wafer with the second wafer; and

separating the bonded first and second wafers into a plurality of die, wherein the separating includes removing material of a separation path of the second wafer, the separation path having a first width, wherein the opening has a second width, and wherein the first width and the second width are selected such that at least one portion of the conductive layer remains on at least one sidewall of a separated die and thereby provides electrical coupling between the first wafer and the second wafer.

8. The method of claim 7 , wherein the second width is wider than the first width.

9. A method for electrically coupling a cap wafer with a device wafer, the method comprising:

bonding the cap wafer with the device wafer using a bonding material, wherein the device wafer comprises a substrate;

forming an opening in the cap wafer and the bonding material in a scribe area of the device wafer to expose a surface of a conductive structure of the device wafer, wherein forming the opening through the cap wafer and the bonding material comprises sawing through the cap wafer and the bonding material in the scribe area of the device wafer; and

forming a conductive layer overlying the cap wafer and the opening in the cap wafer such that the conductive layer forms an electrical contact with the conductive structure of the device wafer thereby electrically coupling the cap wafer with the device wafer.

10. The method of claim 9 , wherein the device wafer comprises a plurality of pads and the method further comprising forming a second opening in the cap wafer to expose the plurality of pads after forming the opening in the cap wafer.

11. The method of claim 9 , wherein the device wafer comprises at least one micro-electro-mechanical systems (MEMS) device.

12. The method of claim 9 further comprising sawing through the device wafer to separate bonded wafers into a plurality of die and wherein each of the plurality of die comprises at least one micro-electro-mechanical systems (MEMS) device.

13. The method of claim 9 further comprising separating the bonded wafers into a plurality of die, wherein the separating includes removing material of a separation path of the device wafer in the scribe area, the separation path having a first width, wherein the opening has a second width, and wherein the first width and the second width are selected such that at least one portion of the conductive layer remains on at least one sidewall of a separated die and thereby continues to provide electrical coupling between the cap wafer and the device wafer.

14. The method of claim 9 , wherein the bonding material is non-conductive.

15. The method of claim 14 , wherein the non-conductive bonding material is glass frit.

16. A method for electrically coupling a first wafer with a second wafer, the method comprising:

bonding the first wafer with the second wafer using a bonding material to form bonded wafers;

forming an opening in the first wafer and the bonding material in a scribe area of the second wafer to expose a surface of a conductive structure of the second wafer;

forming a conductive layer overlying the first wafer and the opening in the first wafer such that the conductive layer forms an electrical contact with the conductive structure of the second wafer thereby electrically coupling the first wafer with the second wafer; and

separating the bonded wafers into a plurality of die, wherein the separating includes removing material of a separation path of the second wafer, the separation path having a first width, wherein the opening has a second width, and wherein the first width and the second width are selected such that at least one portion of the conductive layer remains on at least one sidewall of a separated die and thereby provides an electrical coupling between the first wafer and the second wafer.

17. The method of claim 16 , wherein the second wafer comprises a plurality of pads and the method further comprising forming a second opening in the first wafer to expose the plurality of pads after forming the opening in the first wafer.

18. The method of claim 16 , wherein each of the plurality of die include a cavity defined by a surface of a structure of the first wafer and a surface of a structure of the second wafer.

19. The method of claim 18 , wherein the second wafer comprises a plurality of micro-electro-mechanical systems (MEMS) devices.

20. The method of claim 16 , wherein the bonding material is a non-conductive glass frit.

Assignments (15)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
Reel/Frame 037694/0264 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037355/0723 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 024079/0082 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2009
From: LIU, LIANJUN; KARLIN, LISA H.; MAGNUS, ALAN J.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 023674/0307 →