Field programmable gate array utilizing dedicated memory stacks in a vertical layer format
View Patent ↗A field programmable gate array, an access lead network coupled to the FPGA, and a plurality of memories electrically coupled to the access lead network. The FPGA, access lead network, and plurality of memories are arranged and configured to operate with a variable word width, namely with a word width between 1 and a maximum number of bits. The absolute maximum word width may be as large as m*N where m is the number of word width bits per memory chip and N is the number of memory chips.
1. An electronic module comprising:
a field-programmable gate array (FPGA);
an access lead network electrically connected to the FPGA;
a stack of integrated circuits electrically connected to the access lead network; and
a plurality of input/output (I/O) terminals disposed on a surface of the stack, wherein the I/O terminals are configured to route electrical signals between the stack and the access lead network.
2. The electronic module of claim 1 , wherein the stack of integrated circuits comprises a stack of memory circuits.
3. The electronic module of claim 1 , wherein the FPGA is configured to operate with a variable word width.
4. The electronic module of claim 3 , wherein the variable word width is between 1 and m*N bits, where m represents a number of bits in a word width of each integrated circuit and N represents the total number of the integrated circuits.
5. The electronic module of claim 1 , further comprising a first ball grid array configured to electrically connect the access lead network to the FPGA and a second ball grid array configured to electrically connect the stack of integrated circuits to the FPGA.
6. The electronic module of claim 1 , further comprising a metallized trace configured to electrically connect at least one of the plurality of I/O terminals to the FPGA.
7. The electronic module of claim 6 , wherein the at least one of the plurality of I/O terminals is electrically connected to the metallized trace by a T-connect structure.
8. The electronic module of claim 1 , wherein the stack of integrated circuits comprises a stack of printed circuit board (PCB) assemblies, wherein each integrated circuit of the stack of integrated circuits is connected to a PCB assembly of the stack of PCB assemblies.
9. An electronic module comprising:
a field-programmable gate array (FPGA) electrically connected to a plurality of memory integrated circuits arranged in a stack, wherein the FPGA is configured to simultaneously access each of the plurality of memory integrated circuits and thereby operate with a variable word width.
10. The electronic module of claim 9 , wherein the variable word width is between 1 and m*N bits, where m represents a number of bits in a word width of each memory integrated circuit and N represents the total number of the memory integrated circuits.
11. The electronic module of claim 9 , further comprising an access lead network configured to electrically connect the FPGA to the plurality of memory integrated circuits.
12. The electronic module of claim 11 , wherein the electronic module further comprises a plurality of input/output (I/O) terminals disposed on a surface of the stack, wherein the plurality of I/O terminals are configured to route electrical signals between the plurality of memory integrated circuits and the access lead network.
13. The electronic module of claim 12 , further comprising a metallized trace configured to electrically connect at least one of the plurality of I/O terminals to the FPGA.
14. The electronic module of claim 13 , further comprising a T-connect structure configured to electrically connect the at least one of the plurality of I/O terminals to the metallized trace.
15. The electronic module of claim 11 , further comprising a first ball grid array configured to electrically connect the access lead network to the FPGA and a second ball grid array configured to electrically connect the stack of memory integrated circuits to the FPGA.
16. The electronic module of claim 9 , wherein the stack comprises a plurality of printed circuit board (PCB) assemblies, wherein the plurality of memory integrated circuits is connected to the plurality of PCB assemblies.
17. A method comprising:
electrically connecting a field-programmable gate array (FPGA) to an access lead network; and
electrically connecting a stack of integrated circuits to the access lead network via a plurality of input/output (I/O) terminals disposed on a surface of the stack, wherein the access lead network is configured to route electrical signals between the FPGA and the stack.
18. The method of claim 17 , wherein the FPGA is configured to utilize a variable word width.
19. The method of claim 18 , wherein the variable word width is between 1 and m*N bits, where m represents a number of bits for a word width of each integrated circuit N represents the total number of the integrated circuits.
20. The method of claim 17 , wherein said electrically connecting an FPGA to an access lead network comprises electrically connecting the FPGA to the access lead network using a first ball grid array, and wherein said electrically connecting a stack of integrated circuits to the access lead network comprises electrically connecting the stack of integrated circuits to the access lead network using a second ball grid array.
21. The method of claim 20 , wherein the access lead network comprises a plurality of vias configured to electrically connect the first ball grid array to the second ball grid array.
22. The method of claim 17 , wherein said electrically connecting an FPGA to an access lead network comprises electrically connecting the FPGA to the access lead network using a first pin grid array, and wherein said electrically connecting a stack of integrated circuits to the access lead network comprises electrically connecting the stack of integrated circuits to the access lead network using a second pin grid array.
23. The method of claim 17 , wherein the access lead network comprises a plurality of metallized traces, and wherein said electrically connecting a stack of integrated circuits to the access lead network further comprises electrically connecting the plurality of metallized traces to the plurality of I/O terminals.
24. The method of claim 23 , wherein at least one of the plurality of I/O terminals is electrically connected to at least one of the plurality of metallized traces by a T-connect structure.
25. The method of claim 17 , wherein the plurality of integrated circuits comprise a plurality of vertically-stacked prepackaged IC chips.
26. An electronic module comprising:
a field-programmable gate array (FPGA) electrically connected to a stack of printed circuit board (PCB) assemblies having ball grid array packages connected thereto; and
a plurality of input/output (I/O) terminals disposed on a surface of the stack, wherein the I/O terminals are configured to route electrical signals between the ball grid array packages and the FPGA.
27. The electronic module of claim 26 , further comprising a first memory integrated circuit (IC) mounted to a first side of one of the PCB assemblies.
28. The electronic module of claim 27 , further comprising a second memory IC mounted to a second side of the one of the PCB assemblies.
29. The electronic module of claim 28 , wherein the second side is opposite the first side.
30. The electronic module of claim 26 , wherein the FPGA is configured to operate with a variable word width, wherein the variable word width is between 1 and m*N bits, where m represents a number of bits in a word width of a memory integrated circuit and N represents a number of memory integrated circuits.
31. The electronic module of claim 26 , further comprising a metallized trace configured to electrically connect at least one of the plurality of I/O terminals to the FPGA.
32. The electronic module of claim 31 , wherein the at least one of the plurality of I/O terminals is electrically connected to the metallized trace by a T-connect structure.