Dummy structure for isolating devices in integrated circuits

1. An integrated circuit, comprising:

a first operational device having a first transistor, wherein the first transistor includes a first gate having a metal with a first work function selected from a group consisting of an n-type work function, a p-type work function, and a mid-gap work function;

a second operational device having a second transistor, wherein the second transistor includes a second gate having a metal with a second work function selected from a group consisting of an n-type work function, a p-type work function, and a mid-gap work function; and

an isolation transistor disposed between the first and second transistors, wherein the isolation transistor includes an isolation gate having a metal with a third work function selected from the group consisting of an n-type work function, a p-type work function, and a mid-gap work function;

wherein the mid-gap work function is between an n-type work function and a p-type work function;

wherein the third work function is different from one of the first work function and the second work function.

2. The integrated circuit of claim 1 , wherein the first and second gates of the respective first and second transistors have metals with n-type work functions;

wherein the isolation gate of the isolation transistor has the metal with one of a p-type work function and a mid-gap work function.

3. The integrated circuit of claim 1 , wherein the first and second gates of the respective first and second transistors are doped with a first type dopant, and wherein the isolation gate of the isolation transistor is doped with a second type dopant opposite the first type dopant.

4. The integrated circuit of claim 1 , wherein a channel region of the isolation transistor is different than a channel region of one of the first transistor and the second transistor.

5. The integrated circuit of claim 4 , wherein the channel region of the one of the first and second transistors is doped with a first doping concentration, and wherein the channel region of the isolation transistor is doped with a second doping concentration greater than the first doping concentration.

6. The integrated circuit of claim 1 , wherein the first and second gates of the respective first and second transistors are disposed within an active region;

wherein the isolation gate of the isolation transistor is disposed between the first and second gates and within the active region.

7. The integrated circuit of claim 1 , wherein the first gate is disposed within a first active region and the second gate is disposed within a second active region, the first and second active regions being separated by an isolation region;

wherein the isolation gate is disposed within the first active region;

further including another isolation transistor having another isolation gate disposed within the second active region and disposed between the isolation gate and the second gate.

8. The integrated circuit of claim 1 , wherein the first gate is disposed within a first active region and the second gate is disposed within a second active region, the first and second active regions being separated by an isolation region;

wherein the isolation gate is disposed within the isolation region.

9. An integrated circuit, comprising:

a first operational device having a first gate of a first composition, wherein the first gate includes a first metal with a first work function;

a second operational device having a second gate of the first composition, wherein the second gate includes a second metal with a second work function; and

an isolation gate disposed between the first and second gates, the isolation gate having a second composition different from the first composition, wherein the isolation gate includes a third metal with a third work function;

wherein the third work function is different from one of the first work function and the second work function.

10. The integrated circuit of claim 9 , wherein the first and second work functions are n-type work functions;

wherein the third work function is one of a p-type work function and a mid-gap work function;

wherein the mid-gap work function is between an n-type work function and a p-type work function.

11. The integrated circuit of claim 9 , wherein the first and second gates are doped with a first type dopant, and wherein the isolation gate is doped with a second type dopant opposite the first type dopant.

12. The integrated circuit of claim 9 , wherein the first and second work functions are p-type work functions;

wherein the third work function is one of an n-type work function and a mid-gap work function;

wherein the mid-gap work function is between an n-type work function and a p-type work function.

13. The integrated circuit of claim 9 , wherein the first and second gates are disposed within an active region;

wherein the isolation gate is disposed within the active region.

14. The integrated circuit of claim 9 , wherein the first gate is disposed within a first active region and the second gate is disposed within a second active region, the first and second active regions being separated by an isolation region;

wherein the isolation gate is disposed within the first active region;

further including another isolation gate disposed within the second active region and disposed between the isolation gate and the second gate, the another isolation gate having the second composition.

15. The integrated circuit of claim 9 , wherein the first gate is disposed within a first active region and the second gate is disposed within a second active region, the first and second active regions being separated by an isolation region;

wherein the isolation gate is disposed within the isolation region.

16. An integrated circuit, comprising:

a semiconductor substrate having a first active region and a second active region;

a first field-effect transistor (FET) device disposed within the first active region, the first FET device having a first functional gate electrode;

a second FET device disposed within the second active region, the second FET device having a second functional gate electrode; and

an isolation gate electrode disposed between the first and second functional gate electrodes, wherein the isolation gate electrode has a first conductivity and includes a first metal having a first work function;

wherein the first and second functional gate electrodes have a second conductivity different from the first conductivity and include a second metal having a second work function;

wherein the first work function is different from the second work function.

17. The integrated circuit of claim 16 , wherein the first work function is one of an n-type work function and a mid-gap work function;

wherein the second work function is a p-type work function;

wherein the mid-gap work function is between an n-type work function and a p-type work function.

18. The integrated circuit of claim 16 , wherein the first work function is one of a p-type work function and a mid-gap work function;

wherein the second work function is an n-type work function;

wherein the mid-gap work function is between an n-type work function and a p-type work function.

19. The integrated circuit of claim 16 , wherein the first conductivity is opposite the second conductivity.

20. The integrated circuit of claim 16 , wherein the first and second active regions are a continuous active region, and wherein the isolation gate electrode is disposed within the continuous active region.

21. The integrated circuit of claim 16 , further including:

a shallow trench isolation (STI) disposed between the first and second active regions;

another isolation gate electrode of the first conductivity, the another isolation gate electrode disposed within the first active region;

wherein the isolation gate electrode is disposed within the second active region and disposed between the another isolation gate electrode and the second functional gate electrode.

22. The integrated circuit of claim 16 , wherein the first and second FET devices are one of:

n-type and wherein the first and second FET devices have one of epi silicon carbide (SiC) source/drain features, SiC doped with phosphorous source/drain features, and silicon phosphide (SiP) source/drain features; and

p-type and wherein the first and second FET devices have silicon germanium (SiGe) source/drain features.

23. The integrated circuit of claim 1 , wherein the first and second gates of the respective first and second transistors have metals with p-type work functions;

wherein the isolation gate of the isolation transistor has a metal with one of an n-type work function and a mid-gap work function.