Digital quadrature phase correction
Methods and systems to adjust a phase difference between signals, such as to perform quadrature phase correction. First and second signals are digitally compared, such as with exclusive OR circuitry, to provide a comparison signal having a duty cycle representative of a phase difference between the signals. A phase delay of one or both of the first and second signals is adjusted until the duty cycle of the comparison signal corresponds to a desired phase difference. In a clock and data recovery system, the signals may correspond to a zero degree phase of a first phase interpolator and a ninety degree phase of a second phase interpolator, and digital codes to the first and second phase interpolators may be adjusted to provide a fifty percent duty cycle in the comparison signal.
1. A system, comprising:
first and second phase controllable clock sources to produce respective first and second clock signals;
a digital comparator to generate a comparison signal having a duty cycle representative of a phase difference between the first and second clock signals;
a digital controller to adjust a duty cycle of each of the first and second clock signals, and the phase difference between the first and second clock signals, based on the comparison signal;
a first multiplexer (MUX) to selectively provide the first and second clock signals, and the comparison signal, to the digital controller; and
a calibration system configured to control the first MUX.
2. The system of claim 1 , further comprising:
a clock and data recovery (CDR) system to produce first and second CDR control signals;
a second MUX to provide a selected one of the first CDR control signal and a first output of the duty cycle controller to the first clock source; and
a third MUX to provide a selected one of the second CDR control signal and a second output of the duty cycle controller to the second clock source,
wherein the calibration system is configured to control the first, second, and third MUXs.
3. The system of claim 2 , wherein the calibration system is configured to control the first, second, and third MUXs in a calibration mode, to calibrate one of the phase difference and the duty cycles, so as to cause
the first MUX to provide the first and second clock signals, and the comparison signal, to the duty cycle controller, and
the second and third MUXs to provide the first and second outputs of the duty cycle controller to the first and second clock sources, respectively.
4. The system of claim 3 , wherein the calibration system is further configured, in a normal mode, to cause the second and third MUXs to provide the first and second CDR control signals, respectively, to corresponding ones of the first and second clock sources.
5. The system of claim 1 , wherein each of the first and second phase controllable clock source includes:
a respective phase interpolator; and
a respective duty cycle controllable buffer, following the respective phase interpolator, to adjust the respective duty cycle responsive to a respective duty cycle control signal from the duty cycle controller.
6. The system of claim 1 , wherein the digital controller is configured to adjust the phase difference between the first and second clock signals subsequent to adjustment of the duty cycles of the first and second clock signals.
7. The system of claim 6 , wherein the digital controller is further configured to:
set an initial phase delay of at least one of the first and second clock signals to provide an initial phase difference between the first and second clock signals, subsequent to adjustments of the duty cycles of the first and second clock signals; and
adjust the phase delay of the at least one of the first and second clock signals in response to the duty cycle of the comparison signal to adjust the initial phase difference.
8. The system of claim 7 , wherein the digital controller is further configured to:
adjust the duty cycles of the first and second clock signals to provide a duty cycle of approximately fifty percent in each of the first and second clock signals;
set a phase delay of the at least one of the first and second clock signals to provide an approximately ninety degree initial phase difference between the first and second clock signals; and
adjust the phase delay of the at least one of the first and second clock signals in response to the duty cycle of the comparison signal to provide a duty cycle of approximately fifty percent in the comparison signal.