Method and system for defining generic topologies for use in topology matching engines
Circuit analysis software packages are a significant tool used today in the design of integrated circuits (ICs). Many of the conventional and commercially available simulation or analysis packages, however, are limited to performing static design “checks” using topology based search algorithms to find potential problems in a subject design. Here, a system is provided that allows a user to define parameters that comport with the subject design to generate a set of specific topologies from a set of generic topologies. These generated topologies can then be used to perform a more thorough analysis of the subject design.
1. A device comprising a processor configured to:
receive a circuit design;
receive a list of fundamental devices, wherein at least one fundamental device in the list of fundamental devices is a transistor;
receive a topology map for the circuit design;
retrieve rules based at least in part on the list of fundamental devices and the topology map;
retrieve a set of generic circuit topologies from a topology database, at least one of the generic circuit topologies including at least two fundamental devices in the list of fundamental devices, wherein at least one fundamental device in the at least two fundamental devices is a transistor;
generate a plurality of circuit topologies from the at least one of the generic circuit topologies based at least in part on the retrieved rules, the list of fundamental devices, and the topology map, each of the circuit topologies including the at least two fundamental devices in the list of fundamental devices;
compare at least a portion of the circuit design to the plurality of circuit topologies to identify which of the circuit topologies are present in the circuit design; and
analyze the circuit design based at least in part on the comparison of the portion of the circuit design to the plurality of circuit topologies.
2. The device of claim 1 , wherein the topology map defines nodes that can be shorted together.
3. The device of claim 2 , wherein the processor is further configured to generate permutations for each generic topology based at least in part on the nodes that can be shorted together.
4. The device of claim 1 , wherein the topology map defines nodes that can be shorted to pads.
5. The device of claim 4 , wherein the processor is further configured to generate permutations for each generic topology based at least in part on the nodes that can be shorted to the pads.
6. The device of claim 1 , wherein the topology map defines device sockets.
7. The device of claim 6 , wherein the processor is further configured to:
determine a technology for the circuit design; and
match fundamental devices from the fundamental device list within the technology to the device sockets.
8. The device of claim 7 , wherein the technology is a BiCMOS process technology.
9. The device of claim 1 , wherein the processor is further configured to determine electrostatic discharge (ESD) sensitivity of the circuit design based at least in part on the comparison of the portion of the circuit design to the plurality of circuit topologies.
10. The device of claim 1 , wherein the topology map defines fundamental devices coupled in parallel to one another.
11. The device of claim 1 , wherein the topology map defines fundamental devices coupled in series to one another.
12. A non-transitory computer-readable medium comprising computer code that, when executed by a processor, causes the processor to:
receive a circuit design;
receive a list of fundamental devices;
receive a topology map for the circuit design;
retrieve rules based at least in part on the list of fundamental devices and the topology map;
retrieve a set of generic circuit topologies from a circuit topology database, at least one of the generic circuit topologies including at least two fundamental devices in the list of fundamental devices;
generate a plurality of circuit topologies from the set of generic circuit topologies based at least in part on the retrieved rules, the list of fundamental devices, and the topology map, each of the circuit topologies including the at least two fundamental devices in the list of fundamental devices;
compare at least a portion of the circuit design to the plurality of circuit topologies to identify which of the circuit topologies are present in the circuit design; and
analyze the circuit design based at least in part on the comparison of the portion of the circuit design to the plurality of circuit topologies.
13. The non-transitory computer-readable medium of claim 12 , wherein the topology map defines nodes that can be shorted together.
14. The non-transitory computer-readable medium of claim 13 , wherein the computer code that causes the processor to generate the plurality of circuit topologies from the set of generic circuit topologies includes computer code that, when executed, causes the processor to generate permutations for each generic topology based at least in part on the nodes that can be shorted together.
15. The non-transitory computer-readable medium of claim 12 , wherein the topology map defines nodes that can be shorted to pads.
16. The non-transitory computer-readable medium of claim 15 , wherein the computer code that causes the processor to generate the plurality of circuit topologies from the set of generic circuit topologies includes computer code that, when executed, causes the processor to generate permutations for each generic topology based at least in part on the nodes that can be shorted to the pads.
17. The non-transitory computer-readable medium of claim 12 , wherein the topology map defines device sockets.
18. The non-transitory computer-readable medium of claim 17 , wherein the computer code that causes the processor to generate the plurality of circuit topologies from the set of generic circuit topologies includes computer code that, when executed, causes the processor to:
determine a technology for the circuit design; and
match fundamental devices from the fundamental device list within the technology to the device sockets.
19. The non-transitory computer-readable medium of claim 18 , wherein the technology is a BiCMOS process technology.
20. The non-transitory computer-readable medium of claim 12 , wherein the computer code that causes the processor to analyze the circuit design includes computer code that, when executed, causes the processor to determine ESD sensitivity of the circuit design based at least in part on the comparison of the portion of the circuit design to the plurality of circuit topologies.
21. The non-transitory computer-readable medium of claim 12 , wherein the topology map defines fundamental devices coupled in parallel to one another.
22. The non-transitory computer-readable medium of claim 12 , wherein the topology map defines fundamental devices coupled in series to one another.