Semiconductor memory cell, method for manufacturing the same and method for operating the same
View Patent ↗A semiconductor memory cell, and method of manufacturing a semiconductor memory cell and an method of operating a semiconductor memory cell. A method of operating may include programming a semiconductor memory cell by applying a preset programming voltage to a common source and/or an N-well region, grounding and/or floating a control gate, and/or grounding a word line and/or a bit line. A method of operating may include erasing a semiconductor memory cell by floating and/or grounding a word line, applying a preset erase voltage to a control gate, and/or grounding an N-well, a bit line and/or a common source. A method of operating may include reading a semiconductor memory cell by grounding and/or floating a control gate, applying a preset read voltage to an N-well and/or a common source, grounding a word line, and/or applying a preset drain voltage to a bit line.
1. A method comprising at least one of:
providing a floating gate over a semiconductor substrate including an N-well region and below a bit line, a word line below said floating gate, a common source below said word line, and a control gate connected to said floating gate by a contact through a dielectric;
programming by applying a preset programming voltage to said common source and said N-well region, at least one of grounding and floating said control gate, and grounding said word line and the bit line;
erasing by at least one of floating and grounding said word line, applying a preset erase voltage to said control gate, and grounding said N-well, said bit line and said common source; and
reading by at least one of grounding and floating said control gate, applying a preset read voltage to said N-well and said common source, grounding said word line, and applying a preset drain voltage to said bit line.
2. The method of claim 1 , wherein a voltage between said preset programming voltage applied to said N-well in said programming and a ground voltage applied to said bit line is induced to said floating gate.
3. The method of claim 1 , wherein said erasing comprises a potential of said floating gate coupled by a ground voltage applied to said N-well and a ground voltage applied to said bit line.
4. The method of claim 1 , wherein a programmed reading state comprises current induced from said common source to said bit line.
5. The method of claim 1 , wherein a programmed erasing state comprises substantially no current induced from said common source to said bit line.
6. The method of claim 1 , comprising providing a semiconductor memory cell.