Flash memory device and method of manufacturing the same
View Patent ↗Disclosed is a flash memory device and a method of manufacturing the same. The flash memory device includes a floating gate formed on a semiconductor substrate, a select gate self-aligned on one sidewall of the floating gate, and an ONO pattern interposed between the floating gate and the select gate. A self-aligned split gate structure is formed for an EEPROM tunnel oxide cell flash memory device employing a split gate structure, so that a cell current is constant and the erasing characteristic between cells is uniform, thereby improving the reliability.
1. A method of manufacturing a flash memory device, the method comprising:
forming a floating gate on a semiconductor substrate and a hard mask on the floating gate;
forming an ONO pattern on a sidewall of the floating gate and the hard mask;
forming a polysilicon pattern on the ONO pattern on the sidewall of the floating gate and the hard mask; and
forming a select gate by removing a portion of the polysilicon pattern,
wherein the forming of the ONO pattern comprises:
forming an ONO layer on the semiconductor substrate having the floating gate and the hard mask; and
performing an etch back process for the ONO layer.
2. The method of claim 1 , wherein forming the floating gate on the semiconductor substrate forms one floating gate in each active region of a cell region of the semiconductor substrate, wherein the floating gates are isolated from each other.
3. The method of claim 1 , wherein the forming of the polysilicon pattern comprises:
forming a polysilicon layer on an entire surface of the semiconductor substrate; and
performing an etch back process with respect to the polysilicon layer, thereby exposing the hard mask and remaining the polysilicon layer on the sidewall of the floating gate,
wherein the floating gate and hard mask are formed in plurality, wherein the polysilicon pattern is connected between closely adjacent floating gates.
4. The method of claim 3 , wherein, when forming the select gate by removing the portion of the polysilicon pattern, the portion of the polysilicon pattern removed corresponds to the connected polysilicon pattern between the closely adjacent floating gates.
5. The method of claim 1 , further comprising:
forming an insulating layer on the semiconductor substrate;
forming a gate spacer at one side of the select gate and one side of the floating gate by performing an etch back process with respect to the insulating layer; and
forming a source area in a vicinity of the floating gate and a drain area in a vicinity of the select gate by implanting impurities into the semiconductor substrate, after forming the select gate.
6. A method of manufacturing a flash memory device, the method comprising:
forming a floating gate on a semiconductor substrate and a hard mask on the floating gate;
forming an ONO pattern on a sidewall of the floating gate and the hard mask;
forming a polysilicon pattern on the ONO pattern on the sidewall of the floating gate and the hard mask;
forming a select gate by removing a portion of the polysilicon pattern;
forming an insulating layer on the semiconductor substrate;
forming a gate spacer at one side of the select gate and one side of the floating gate by performing an etch back process with respect to the insulating layer; and
foaming a source area in a vicinity of the floating gate and a drain area in a vicinity of the select gate by implanting impurities into the semiconductor substrate, after forming the select gate.
7. A method of manufacturing a flash memory device, the method comprising:
forming a floating gate on a semiconductor substrate and a hard mask directly on a top surface of the floating gate;
forming an ONO pattern on a sidewall of the floating gate and the hard mask;
forming a polysilicon pattern on the ONO pattern on the sidewall of the floating gate and the hard mask; and
forming a select gate by removing a portion of the polysilicon pattern.
8. The method of claim 7 , wherein the forming of the ONO pattern comprises:
forming an ONO layer on the semiconductor substrate having the floating gate and the hard mask; and
performing an etch back process for the ONO layer.
9. The method of claim 7 , wherein forming the floating gate on the semiconductor substrate forms one floating gate in each active region of a cell region of the semiconductor substrate, wherein the floating gates are isolated from each other.
10. The method of claim 7 , wherein the forming of the polysilicon pattern comprises:
forming a polysilicon layer on an entire surface of the semiconductor substrate; and
performing an etch back process with respect to the polysilicon layer, thereby exposing the hard mask and remaining the polysilicon layer on the sidewall of the floating gate,
wherein the floating gate and hard mask are formed in plurality, wherein the polysilicon pattern is connected between closely adjacent floating gates.
11. The method of claim 10 , wherein, when forming the select gate by removing the portion of the polysilicon pattern, the portion of the polysilicon pattern removed corresponds to the connected polysilicon pattern between the closely adjacent floating gates.
12. The method of claim 11 , further comprising:
forming an insulating layer on the semiconductor substrate;
forming a gate spacer at one side of the select gate and one side of the floating gate by performing an etch back process with respect to the insulating layer; and
forming a source area in a vicinity of the floating gate and a drain area in a vicinity of the select gate by implanting impurities into the semiconductor substrate, after forming the select gate.