Lateral double diffused metal oxide semiconductor
View Patent ↗Disclosed are lateral double diffused metal oxide semiconductor (LDMOS) transistors having a uniform threshold voltage and methods for manufacturing the same. The methods include forming a polysilicon layer over the semiconductor substrate including a shallow trench isolation region, etching a portion of the polysilicon layer over an active region, implanting first conductive-type impurity ions using the polysilicon layer as a mask to form a first conductive-type body region, implanting second conductive-type impurity ions using the polysilicon layer as a mask to form a second conductive-type channel region in the first conductive-type body region, removing the polysilicon layer, forming gate electrodes in the polysilicon-free region, and forming a source region and a drain region in the first conductive-type body region using the gate electrode and the shallow trench isolation as ion-implantation masks.
1. A method for manufacturing a lateral double diffused metal oxide semiconductor transistor, comprising:
forming a polysilicon layer over the entire surface of a semiconductor substrate, including first and second shallow trench isolation regions that define one or more active regions and a plurality of device-isolation regions;
etching a portion of the polysilicon layer over one of said active region(s);
implanting first conductive-type impurity ions using the polysilicon layer as a mask to form a first conductive-type body region;
implanting second conductive-type impurity ions using the polysilicon layer as a mask to form a second conductive-type channel region in the first conductive-type body region;
removing the polysilicon layer;
forming first and second gate electrodes;
forming a source region in the first conductive-type body region; and
forming first and second drain regions in the semiconductor substrate.
2. The method according to claim 1 , wherein the first conductive-type impurity is a p-type impurity, and the second conductive-type impurity is an n-type impurity.
3. The method according to claim 1 , wherein forming the first and second gate electrodes comprises:
forming an oxide film over the entire surface of the etched polysilicon layer and in a space in the polysilicon layer;
planarizing the resulting structure until the etched polysilicon layer is exposed;
etching the resulting structure to remove only the polysilicon layer;
forming a gate electrode layer;
removing the oxide film by etching; and
patterning the gate electrode layer to form the first and second gate electrodes.
4. The method according to claim 3 , wherein etching the polysilicon comprises dry-etching.
5. The method according to claim 3 , wherein etching the oxide film comprises wet-etching using hydrofluoric acid.
6. The method according to claim 3 , wherein a distance between an edge of the second conductive-type channel region and an edge of the first conductive-type body region is uniform.
7. The method according to claim 1 , wherein a distance between an edge of the first gate electrode and a nearest edge of the second conductive-type channel region is substantially the same as a distance between an edge of the second gate electrode and a nearest edge of the second conductive-type channel region.
8. The method according to claim 1 , wherein one end of the first gate electrode extends over a surface of the second conductive-type channel region, and an opposite end of the first gate electrode extends over the first shallow trench isolation region, and the second gate electrode extends over a surface of the second conductive-type channel region, and an opposite end of the second gate electrode extends over the second shallow trench isolation region.
9. The method according to claim 1 , further comprising implanting first conductive-type impurity ions adjacent to the source region to form a source contact region.
10. The method according to claim 1 , further comprising forming a gate oxide film over the entire surface of the semiconductor substrate prior to formation of the polysilicon layer.