IP Library Granted Patent US 9,087,926
Granted Patent B2
US 9,087,926 · App. 12/646,324 · Granted Jul 21, 2015

Low capacitance semiconductor device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,087,926
App. No.
12/646,324
Granted
Jul 21, 2015
Kind
B2
Abstract

A semiconductor device includes a diode, a passivation layer and a conductive layer. The diode includes an epitaxial layer on a semiconductor substrate, and first and second diode contacts on different planes. The passivation layer has a planar top surface, and includes multiple consecutive layers of a benzocyclobutene (BCB) material formed on the diode, an aggregate thickness of the passivation layer exceeding a thickness of the epitaxial layer. The conductive layer is formed on the top surface of passivation layer, the conductive layer connecting with the first and the second diodes contact through first and second openings in the passivation layer, respectively. The passivation layer enhances a capacitive isolation between the conductive layer and the diode.

Claims (38)

1. A semiconductor device, comprising:

a diode comprising an epitaxial layer on a semiconductor substrate, and first and second diode contacts on different planes;

a passivation layer having a planar top surface, the passivation layer comprising a first sub-layer of a benzocyclobutene (BCB) material formed on the diode and a second sub-layer of BCB material formed on the first sub-layer with no intervening layer, an aggregate thickness of the passivation layer exceeding a thickness of the epitaxial layer; and

a conductive layer formed on the top surface of passivation layer, the conductive layer connecting with the first and second diode contacts through first and second openings in the passivation layer, respectively,

wherein the passivation layer provides a capacitive isolation between the conductive layer and the diode.

2. The semiconductor device of claim 1 , wherein the different planes of the first diode contact and the second diode are separated by at least the thickness of the epitaxial layer.

3. The semiconductor device of claim 1 , wherein the first diode contact is formed on the epitaxial layer and the second diode contact is formed on the semiconductor substrate, the conductive layer connecting with the second diode contact through the second opening in the passivation layer and a via in the epitaxial layer.

4. The semiconductor device of claim 3 , wherein a portion of the via in the epitaxial layer is filled with the BCB material.

5. The semiconductor device of claim 3 , wherein the conductive layer comprises a first bond pad connecting with the first diode contact through the first opening in the passivation layer, and a second bond pad connecting with the second diode contact through the second opening in the passivation layer and the via in the epitaxial layer.

6. The semiconductor device of claim 1 , wherein the epitaxial layer is included in a mesa formed on the substrate, and

wherein the first diode contact is formed on a top surface of the mesa and the second diode contact is formed on the semiconductor substrate.

7. The semiconductor device of claim 6 , wherein the conductive layer comprises a first bond pad connecting with the first diode contact through the first opening in the passivation layer, and a second bond pad connecting with the second diode contact through the second opening in the passivation layer.

8. The semiconductor device of claim 1 , wherein the aggregate thickness of the passivation layer is greater than a maximum possible thickness of a single layer of the BCB material applied using a spin-on application.

9. The semiconductor device of claim 1 , wherein the aggregate thickness of the passivation layer is greater than about 10 μm.

10. The semiconductor device of claim 1 , wherein the conductive layer comprises a plurality of co-planar bond pads respectively connected to the first diode contact and the second diode contact.

11. The semiconductor device of claim 10 , wherein the semiconductor device is configured for flip-chip bonding to an electrical circuit through the plurality of bond pads.

12. The semiconductor device of claim 10 , wherein the first diode contact is an anode contact, and the second diode contact is a cathode contact.

13. The semiconductor device of claim 10 , wherein the first diode contact is a cathode contact, and the second diode contact is an anode contact.

14. A semiconductor diode device, comprising:

an epitaxial layer on a semiconductor substrate;

a first passivation layer on the epitaxial layer;

an anode contact on the epitaxial layer;

a cathode contact on the semiconductor substrate;

a second passivation layer having a planar top surface, the second passivation layer comprising multiple consecutive sub-layers of a low-k dielectric material formed on the epitaxial layer, with no intervening layer between the consecutive sub-layers, an aggregate thickness of the second passivation layer exceeding a thickness of the epitaxial layer;

an anode bond pad on the top surface of second passivation layer, the anode bond pad connecting with the anode contact through a first opening in the second passivation layer; and

a cathode bond pad on the top surface of second passivation layer, the cathode bond pad connecting with the cathode contact through a second opening in the second passivation layer, the cathode bond pad being on substantially the same plane as the anode bond pad.

15. The semiconductor diode device of claim 14 , wherein the low-k dielectric material comprises benzocyclobutene (BCB).

16. The semiconductor diode device of claim 14 , wherein the aggregate thickness of the second passivation layer is greater than about 10 μm.

17. The semiconductor diode device of claim 14 , wherein the epitaxial layer is included in a mesa formed on the semiconductor substrate, and the anode contact is formed on a top surface of the mesa.

18. A semiconductor diode device, comprising:

a semiconductor substrate defining a pit filled with a low-k dielectric material;

an anode contact on the semiconductor substrate adjacent the pit;

a cathode contact on the semiconductor substrate adjacent the anode contact;

an anode bond pad connecting with the anode contact through a first opening in a passivation layer, the anode bond pad comprising an extended portion extending over a surface of the low-k dielectric material in the pit; and

a cathode bond pad connecting with the cathode contact through a second opening in the passivation layer, the cathode bond pad being on substantially the same plane as the anode bond pad.

19. The semiconductor diode device of claim 18 , wherein the low-k dielectric material comprises benzocyclobutene (BCB).

20. The semiconductor diode device of claim 18 , further comprising:

a coating of the low-k dielectric material covering at least a portion of the anode bond pad and the cathode bond pad over an active region of the semiconductor diode device.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
MERGER Recorded May 7, 2013
From: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 030369/0471 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2009
From: SNYDER, RICK D.
To: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.
Reel/Frame 023705/0383 →