Semiconductor integrated circuit
View Patent ↗A semiconductor integrated circuit according to an exemplary embodiment of the present invention includes an I/O buffer provided in a semiconductor chip, single-layer pads, and multilayer pads. The single-layer pads are formed above the I/O buffer. The multilayer pads are formed above the I/O buffer separately from the single-layer pads. The single-layer pads are pads dedicated to bonding, and the multilayer pads are pads on which both probing and bonding are performed.
1. A semiconductor integrated circuit comprising:
an I/O buffer provided in a semiconductor chip;
single-layer pads formed above the I/O buffer; and
multilayer pads formed above the I/O buffer separately from the single-layer pads, such that the single-layer pads and the multilayer pads are separately arranged, thereby enhancing the degree of freedom in the layout of pads in the semiconductor integrated circuit.
2. The semiconductor integrated circuit according to claim 1 , wherein the single-layer pads are pads dedicated to bonding.
3. The semiconductor integrated circuit according to claim 1 , wherein the multilayer pads are pads on which at least probing is performed.
4. The semiconductor integrated circuit according to claim 3 , wherein the multilayer pads are pads on which bonding is further performed.
5. The semiconductor integrated circuit according to claim 1 , wherein the multilayer pads each have a probe mark formed thereon.
6. The semiconductor integrated circuit according to claim 1 , wherein the single-layer pads and the multilayer pads are arranged in a staggered manner, and the single-layer pads are arranged inside the multilayer pads of the semiconductor chip.
7. A semiconductor integrated circuit comprising:
an I/O buffer provided in a semiconductor chip;
single-layer pads formed above the I/O buffer; and
multilayer pads formed above the I/O buffer separately from the single-layer pads, wherein the single-layer pads and the multilayer pads are arranged in a staggered manner, and the single-layer pads are arranged inside the multilayer pads of the semiconductor chip, the semiconductor integrated circuit further comprising an I/O buffer power supply reinforcing line connected to the I/O buffer, wherein the single-layer pads are formed above the I/O buffer power supply reinforcing line.
8. The semiconductor integrated circuit according to claim 7 , further comprising an I/O looped power supply line connected to the I/O buffer, wherein the single-layer pads are formed above the I/O looped power supply line.
9. A semiconductor integrated circuit comprising:
an I/O buffer provided in a semiconductor chip;
single-layer pads formed above the I/O buffer; and
multilayer pads formed above the I/O buffer separately from the single-layer pads, wherein the single-layer pads and the multilayer pads are arranged in a staggered manner, and the single-layer pads are arranged inside the multilayer pads of the semiconductor chip, the semiconductor integrated circuit further comprising:
an internal core circuit formed inside the single-layer pads and the multilayer pads of the semiconductor chip; and
an internal core power supply reinforcing line connected to the internal core circuit,
wherein the single-layer pads are formed above the internal core power supply reinforcing line.
10. A semiconductor integrated circuit comprising:
an I/O buffer provided in a semiconductor chip;
single-layer pads formed above the I/O buffer; and
multilayer pads formed above the I/O buffer separately from the single-layer pads, the semiconductor integrated circuit further comprising:
an internal core circuit formed inside the multilayer pads of the semiconductor chip; and
an internal core power supply reinforcing line connected to the internal core circuit, wherein the multilayer pads are arranged along a peripheral portion of the semiconductor chip, and the single-layer pads are formed above the internal core power supply reinforcing line.