Line-edge roughness improvement for small pitches
View Patent ↗A method for mitigating line-edge roughness on a semiconductor device. The method includes line-edge roughness mitigation techniques in accordance with embodiments of the present invention. The techniques include: reducing the SiON film thickness below a conventional thickness; increasing the photoresist thickness above a conventional thickness; etching the SiON film with an etch bias power less than a conventional wattage amount with an overetch percentage less than a conventional overetch percentage; removing the SiON film layer immediately after completion of the amorphous carbon film layer etching; and lowering the lower electrode temperature below a conventional temperature.
1. A method for fabricating a semiconductor device, the method comprising:
providing a semiconductor substrate with a plurality of mask layers formed on the semiconductor substrate, wherein the plurality of mask layers comprise: an organic antireflective coating/silicon oxynitride (oARC/SiON) film stack for mitigating line-edge roughness in the semiconductor device;
providing a patterned photoresist layer over the plurality of mask layers formed over the substrate, wherein the patterned photoresist layer is in contact with the oARC/SiON film stack; and
etching the plurality of mask layers formed on the substrate, using the patterned photoresist layer as an etching mask to form at least one trench in the plurality of mask layers, wherein the oARC/SiON film stack is etched with an overetch that is less than 30 percent, wherein the overetch of less than 30 percent prevents resulting increase in top and bottom line width roughness while cleaning out the SiON, and wherein a higher percentage of SiON overetch provides undesirable increase in to and bottom average line width roughness.
2. The method of claim 1 , wherein the patterned photoresist comprises 193 nanometer (nm) photoresist, for immersion argon fluoride (ArF) ultra violet lithography, wherein the pattern is formed using about 193 nm wavelength radiation.
3. The method of claim 2 , wherein the photoresist is approximately 1150 angstroms (Å) thick.
4. The method of claim 1 , wherein the SiON film layer is approximately 225 angstroms (Å) thick.
5. The method of claim 1 , wherein a bottom electrode in contact with the semiconductor device has a temperature of approximately 10-15 degrees C. during at least the oARC/SiON film etching.
6. The method of claim 5 , wherein the bottom electrode temperature is approximately 10 degrees C.
7. The method of claim 1 further comprising providing an amorphous carbon film layer, wherein the SiON film layer is removed after a plasma etch has passed through the amorphous carbon film layer.
8. The method of claim 1 , wherein a plasma for etching the SiON film layer comprises hydrogen.
9. The method of claim 1 , wherein the etching of the plurality of mask layers form at least one of a group consisting of vias, trenches, and semiconductor devices.
10. A method for fabricating a semiconductor device, the method comprising:
providing a substrate with a plurality of mask layers formed on the substrate, wherein the plurality of mask layers comprise: an organic antireflective coating/silicon oxynitride (oARC/SiON) film stack for mitigating the edge roughness in the semiconductor device;
providing a patterned photoresist layer over the plurality of mask layers formed over the substrate, wherein the patterned photoresist layer is in contact with the oARC/SiON film stack; and
etching the plurality of mask layers formed on the substrate, using the patterned photoresist layer as an etching mask to form at least one trench in the plurality of mask layers, wherein the etch bias power for the oARC/SiON film stack etching is approximately 200 watts when the overetch is approximately 30 percent, wherein the overetch of less than 30 percent prevents resulting increase in top and bottom line width roughness while cleaning out the SiON, and wherein a higher percentage of SiON overetch provides undesirable increase in top and bottom average line width roughness.
11. The method of claim 10 , wherein the SiON film layer thickness is approximately 225 angstroms (Å).
12. The method of claim 10 , wherein the patterned photoresist comprises 193 nanometer (nm) photoresist, for immersion argon fluoride (ArF) ultra violet lithography, wherein the pattern is formed using about 193 nm wavelength radiation.
13. The method of claim 10 , wherein the bottom electrode in contact with the semiconductor device has a temperature of approximately 10-15 degrees C. during at least the oARC/SiON film etching.
14. The method of claim 13 , wherein the bottom electrode temperature is 10 degrees C.
15. The method of claim 10 further comprising providing an amorphous carbon film layer, wherein the SiON film layer is removed after a plasma etch has passed through the amorphous carbon film layer.
16. The method of claim 10 , wherein the photoresist is approximately 1150 angstroms (Å) thick.
17. The method of claim 10 , wherein a plasma for etching the SiON film layer comprises hydrogen.
18. The method of claim 10 , wherein the etching of the plurality of mask layers forms at least one of a group consisting of vias, trenches, and semiconductor devices.