Semiconductor device and method of manufacturing the same

1. A method comprising:

forming a semiconductor substrate including a CMOS region and a bipolar region;

forming a first isolation layer in the CMOS region and second and third isolation layers in the bipolar region;

forming a first P well at one side of the first isolation layer and a first N well at an opposite side of the first isolation layer;

forming a deep P well in the bipolar region and a second N well in the deep P well corresponding to one side of the second isolation layer;

forming a first gate in the first N well and a second gate in the first P well;

forming a first source/drain by implanting second type impurities into the first N well, and an emitter and a collector by implanting second type impurities into the deep P well and the second N well at both sides of the second isolation layer; and then

forming a second source/drain by implanting the second type impurities into the first P well, and a base by implanting the second type impurities into the second N well at one side of the third isolation layer.

2. The method of claim 1 , further comprising forming a deep N well at a deep region of the bipolar region before forming the deep P well.

3. The method of claim 1 , wherein the emitter and the collector include P type impurities and the base includes N type impurities so that a PNP bipolar transistor is formed.

4. The method of claim 1 , further comprising:

forming a first photoresist pattern over the semiconductor substrate to selectively expose the first N well and portions of the deep P well and the second N well at both sides of the second isolation layer; and then

forming first LDD regions in the first N well corresponding to both sides of the first gate, and second type shallow doped layers at a portion of the second N well and the deep P well using the first photoresist pattern as an ion implantation mask, after forming the first and second gates.

5. The method of claim 4 , wherein forming the first source/drain in the first N well and the forming of the emitter and the collector in emitter and collector regions comprises:

forming a third photoresist pattern using a mask identical to a mask of the first photoresist pattern; and then

forming the first source/drain below the first LDD region and a second type deep doped layer below the second type shallow doped layer using the third photoresist pattern as an ion implantation mask.

6. The method of claim 1 , further comprising:

forming a second photoresist pattern to expose the first P well of the semiconductor substrate and the second N well at one side of the third isolation layer; and

forming second LDD regions at the first P well corresponding to both sides of the second gate, and a first type shallow doped layer at a portion of the second N well by using the second photoresist pattern as an ion implantation mask, after forming the first and second gates.

7. The method of claim 6 , wherein forming of the second source/drain in the first P well, and the base in the base region comprises:

forming a fourth photoresist pattern using a mask identical to a mask of the second photoresist pattern; and then

forming the second source/drain below the second LDD region and a first type deep doped layer below the first type shallow doped layer using the fourth photoresist pattern as an ion implantation mask.

8. The method of claim 5 , further comprising:

forming an interlayer dielectric layer; and then

forming an emitter electrode, a collector electrode and a base electrode connected with the emitter, the collector, and the base, respectively, through the interlayer dielectric layer, after forming the base in the base region.