Semiconductor device with buried bit lines interconnected to one-side-contact and fabrication method thereof
A semiconductor device with reduced resistance of a buried bit line, and a method for fabricating the same. The method for fabricating a semiconductor device includes etching a semiconductor substrate to form a plurality of active regions which are separated from one another by trenches formed in between, forming a side contact on a sidewall of each active region, and forming metal bit lines, each filling a portion of a respective trench and connected to the side contact.
1. A method for fabricating a semiconductor device, comprising:
etching a semiconductor substrate to form a plurality of active regions which are separated from one another by trenches formed in between;
forming a side contact on a sidewall of each active region;
forming metal bit lines, each filling a portion of each trench and connected to the side contact;
forming a plurality of active pillars which are separated from one another in a damascene pattern over each active region by etching the active regions; and
forming word lines extended in a direction crossing the metal bit lines and positioned on sidewalls of the active pillars by forming a conductive layer filling the damascene pattern and etching the conductive layer using a spacer as an etch barrier.
2. The method of claim 1 , wherein the active regions are formed in a line shape, and the side contact and the metal bit line are formed in parallel to the active regions.
3. The method of claim 1 , wherein the side contact comprises a metal silicide.
4. The method of claim 1 , wherein the metal bit line is formed by stacking a titanium nitride layer and a tungsten layer (TiN/W).
5. The method of claim 1 , further comprising:
forming a capacitor with a storage node connected to an upper portion of the active pillar.
6. A method for fabricating a semiconductor device, comprising:
etching a semiconductor substrate to form a plurality of active regions separated from one another by trenches formed in between;
forming a sacrificial layer gap-filling the trenches, wherein a protrusion is formed over each active region from the formation of the sacrificial layer;
forming an insulation layer pattern contacting a sidewall of the protrusion; etching the sacrificial layer by using the insulation layer pattern as an etch barrier;
forming contact regions each opening a sidewall of the active regions; forming side contacts each filling the contact regions;
forming metal bit lines, each being connected to each side contact and filling a portion of each trench;
forming a plurality of active pillars which are separated from one another in a damascene pattern over each active region by etching the active regions; and
forming word lines extended in a direction crossing the metal bit lines and positioned on sidewalls of the active pillars by forming a conductive layer filling the damascene pattern and etching the conductive layer using a spacer as an etch barrier.
7. The method of claim 6 , wherein the insulation layer pattern comprises an undoped insulation layer.
8. The method of claim 6 , wherein the trenches are formed by using a hard mask layer as an etch barrier and etching the semiconductor substrate, and the protrusion is formed of the hard mask layer.
9. The method of claim 6 , wherein the metal bit lines are formed by stacking a titanium nitride layer and a tungsten layer (TiN/W).
10. The method of claim 6 , wherein the side contact comprises a metal silicide.
11. The method of claim 6 , wherein the active regions are formed in a line shape, and the side contact and the metal bit lines are formed to be arranged in parallel to the active regions.
12. The method of claim 6 , further comprising:
forming a capacitor with a storage node connected to an upper portion of the active pillar.
13. The method of claim 6 , before the formation of the sacrificial layer, further comprising:
forming a sidewall oxide layer on sidewalls of each active region through a sidewall oxidation; and
forming a first liner nitride layer covering a resultant substrate including the active regions.
14. A method for fabricating a semiconductor device, comprising:
etching a semiconductor substrate to form a plurality of active regions separated from one another by trenches formed in between;
forming a sidewall oxide layer on sidewalls of each active region through a sidewall oxidation;
forming a first liner nitride layer covering a resultant substrate including the active regions;
forming a sacrificial layer gap-filling the trenches, wherein a protrusion is formed over each active region from the formation of the sacrificial layer;
forming an insulation layer pattern contacting a sidewall of the protrusion: etching the sacrificial layer by using the insulation layer pattern as an etch barrier;
forming contact regions each opening a sidewall of the active regions;
forming side contacts each filling the contact regions; and
forming metal bit lines, each being connected to each side contact and filling a portion of each trench,
wherein the forming of the contact regions comprises:
removing the sacrificial layer;
forming an amorphous silicon layer gap-filling the trenches;
performing an etch-back process to the amorphous silicon layer;
forming a second liner nitride layer on a sidewall of the active region to expose a surface of the amorphous silicon layer obtained after the etch-back process;
forming a line-shaped opening by removing the amorphous silicon layer; and
selectively etching the sidewall oxide layer through the opening.
15. The method of claim 14 , wherein the sidewall oxide layer is selectively etched through the opening by performing a wet cleaning process.
16. A method for fabricating a semiconductor device, comprising:
etching a semiconductor substrate to form a plurality of active regions separated from one another by trenches formed in between;
forming a sacrificial layer gap-filling the trenches, wherein a protrusion is formed over each active region from the formation of the sacrificial layer;
forming an insulation layer over the substrate including the protrusion; implanting a dopant into the insulation layer through a tilt ion implantation process;
forming an insulation layer pattern by selectively removing a portion of the insulation layer where the dopant is implanted;
etching the sacrificial layer by using the insulation layer pattern as an etch barrier;
forming contact regions each opening a sidewall of the active regions;
forming side contacts each filling the contact regions;
forming metal bit lines, each being connected to each side contact and filling a portion of each trench;
forming a plurality of active pillars which are separated from one another in a damascene pattern over each active region by etching the active regions; and
forming word lines extended in a direction crossing the metal bit lines and positioned on sidewalls of the active pillars by forming a conductive layer filling the damascene pattern and etching the conductive layer using a spacer as an etch barrier.
17. The method of claim 16 , wherein the insulation layer pattern comprises an undoped insulation layer.
18. The method of claim 16 , wherein the dopant comprises boron.
19. The method of claim 16 , wherein the portion of the insulation layer where the dopant is implanted is selectively removed through a wet cleaning process or a dry cleaning process.