Controlling AC disturbance while programming
View Patent ↗A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.
1. A method that facilitates reducing disturbances during an operation associated with a memory, comprising:
pre-charging bit lines associated with a selected memory cell and neighbor memory cells of the selected memory cell in a block in a memory array during an AC operation on the selected memory cell to reduce disturbance in a neighbor memory cell adjacent to the selected memory cell in the block; and
changing voltage levels for terminals of the selected memory cell based in part on a specified sequence to reduce disturbances in the selected memory cell.
2. The method of claim 1 , further comprising changing the voltage at a source terminal of the selected memory cell to a predetermined voltage level based in part on the specified sequence.
3. The method of claim 1 , further comprising changing the voltage at a drain terminal of the selected memory cell to a predetermined voltage level based in part on the specified sequence.
4. The method of claim 1 , further comprising setting respective voltages at a source and drain terminal of the selected memory cell to a respective predetermined voltage level at substantially the same time.
5. The method of claim 1 , further comprising specifying a voltage to pre-charge the bit lines in the memory array.
6. The method of claim 5 , further comprising at least one of externally supplying or internally deriving the voltage.
7. The method of claim 1 , further comprising discharging the bit lines to ground potential on completion of the AC operation.
8. The method of claim 1 , further comprising performing at least one of a program, a read, or an erase operation.
9. A method for mitigating disturbances in connection with memory operations, comprising:
pre-charging bit lines associated with a selected memory cell;
pre-charging bit lines associated with a neighbor memory cell that is adjacent to the selected memory cell; and
modifying at least one voltage level for terminals of the selected memory cell based in part on a disturbance-reduction sequence.
10. The method of claim 9 , further comprising pre-charging at least one terminal pair associated with the selected memory cell or the neighbor memory cell substantially contemporaneously, wherein the at least one terminal pair includes a source terminal and a drain terminal.
11. The method of claim 9 , further comprising pre-charging bit lines prior to a memory operation on the selected memory cell.
12. The method of claim 9 , further comprising powering pre-charging by way of either or both an internal circuit or an external power source.