Calibration circuit, semiconductor device including the same, and data processing system

1. A semiconductor device adjusting an impedance level of an output buffer, comprising:

a replica buffer circuit including a circuit configuration substantially identical to the output buffer;

a counter circuit changing an impedance code to vary an impedance level of the replica buffer;

a latch circuit temporarily holding the impedance code in response to a control signal; and

an end-determining circuit producing the control signal in response to a lapse of a predetermined period from issuance of a calibration command, irrespective of a fact that the replica buffer has not yet reached a desirable impedance level.

2. The semiconductor device as claimed in claim 1 , wherein the end-determining circuit further produces the control signal in response to an impedance level of the replica buffer reaching the desirable impedance level.

3. The semiconductor device as claimed in claim 2 , wherein the end-determining circuit generates a first internal signal provided correspondingly to the lapse of the predetermined period from issuance of the calibration command and a second internal signal provided correspondingly to the impedance level of the replica buffer reaching the desirable impedance level, and wherein the end-determining circuit includes an OR circuit which receives the first and second internal signals to produce the control signal.

4. The semiconductor device as claimed in claim 1 , further comprising a start-code generating circuit receiving the impedance code from the latch circuit as a start impedance code, and the start-code generating circuit supplying the start impedance code to the counter circuit when the start-code generating circuit receives the calibration command.

5. The semiconductor device as claimed in claim 1 , wherein the latch circuit supplies the output buffer with the impedance code.

6. The semiconductor device as claimed in claim 1 , further comprising a calibration terminal connected to a calibration resistor, the desirable impedance level being related to the calibration resistor.

7. The semiconductor device as claimed in claim 1 , wherein the replica buffer circuit includes a first replica buffer of which configuration is substantially identical to that of one of pull-up and pull-down circuits each included in the output buffer and a second replica buffer of which configuration is substantially identical to that of an alternate one of the pull-up and pull-down circuits each included in the output buffer, the impedance code includes a first impedance code portion and a second impedance code portion defining impedance of the first and second replica buffers respectively, and the latch circuit includes first and second latch circuits holding the first and second impedance codes, respectively.

8. The semiconductor device as claimed in claim 7 , wherein the counter circuit includes first and second operation modes which change, the first and second impedance code portions, respectively.

9. The semiconductor device as claimed in claim 8 , wherein the predetermined period is substantially half a calibration period, and the end-determining circuit switches first and second operation modes from one to the other in response to a lapse of the predetermined period from a start of a calibration operation.

10. The semiconductor device as claimed in claim 8 , wherein the predetermined period is substantially identical to a calibration period, and the first and second operation modes are switched each time the calibration command is issued.

11. A method for a semiconductor device, comprising:

changing an impedance code to vary an impedance level of a replica buffer;

temporarily holding the impedance code in response to a first control signal;

producing a second control signal in response to a lapse of a predetermined period from issuance of a calibration command, irrespective of a fact that the replica buffer has not yet reached a desirable impedance level; and

producing the first control signal in response to the second control signal.

12. The method as claimed in claim 11 , further comprising producing a third control signal in response to the replica buffer reaching a predetermined impedance level, the first control signal being further produced in response to the third control signal.

13. The method as claimed in claim 12 , further comprising performing a logic operation on the second and third control signals to produce the first control signal.