Method for fabricating thin film transistor
A method for fabricating a thin film transistor (TFT) on a substrate includes forming a gate electrode; forming a semiconductor layer being insulated from the gate electrode and partially overlapped with the gate electrode; sequentially forming first and second gate insulating layers between the gate electrode and the semiconductor layer, wherein the first gate insulating layer is formed of a material different from the second gate insulating layer and at least one of the first and second gate insulating layers includes a sol-compound; and forming source and drain electrodes at both sides of the semiconductor layer.
1. A method for fabricating a thin film transistor (TFT) on a substrate, comprising:
forming a gate electrode;
forming a semiconductor layer being insulated from the gate electrode and partially overlapped with the gate electrode;
sequentially forming first and second gate insulating layers between the gate electrode and the semiconductor layer, wherein the first gate insulating layer is formed of a material different from the second gate insulating layer and at least one of the first and second gate insulating layers include a sol-gel compound, wherein the sol-gel compound includes silicon alkoxide and metal alkoxide; and
forming source and drain electrodes at both sides of the semiconductor layer.
2. The method of claim 1 , wherein metal particles of the metal alkoxide includes at least any one of titanium Ti, zirconium Zr, yttrium Y, aluminum Al, hafnium Hf, calcium Ca, and magnesium Mg.
3. The method of claim 1 , wherein the metal alkoxide includes a material having a dielectric constant of about 7 or more.
4. The method of claim 1 , wherein the second gate insulating layer includes an inorganic insulating material.
5. The method of claim 4 , wherein the second gate insulating layer includes silicon nitride or silicon oxide.
6. The method of claim 4 , wherein the semiconductor layer includes amorphous silicon.
7. The method of claim 1 , wherein the second gate insulating layer includes an organic polymer material.
8. The method of claim 7 , wherein the second gate insulating layer includes at least any one of PVA (polyvinyl alcohol), PVAc (polyvinyl acetate), PVP (polyvinyl phenol) and PMMA (polyvinyl methyl methacrylate).
9. The method of claim 7 , wherein the semiconductor layer is formed of a pentacene-based or thiophene-based material.
10. The method of claim 1 , wherein the sol-gel compound has a dielectric constant and transmittance that change according to a content ratio of silicon alkoxide and metal alkoxide.
11. The method of claim 1 , wherein the sol-gel compound is formed by any one of printing, coating and deposition processes.
12. The method of claim 1 , wherein forming the gate electrode, the semiconductor layer, the gate insulating layer, and the source and drain electrodes includes:
forming the gate electrode on the substrate;
forming the gate insulating layer on an entire surface of the substrate including the gate electrode;
forming the semiconductor layer on the gate insulating layer above the gate electrode; and
forming the source and drain electrodes at both sides of the semiconductor layer.
13. The method of claim 1 , wherein forming the gate electrode, the semiconductor layer, the gate insulating layer, and the source and drain electrodes includes:
forming the source and drain electrodes on the substrate;
forming the semiconductor layer being overlapped with the source and drain electrodes in-between;
forming the gate insulating layer on an entire surface of the substrate including the semiconductor layer; and
forming the gate electrode on the gate insulating layer above the semiconductor layer.