Field programmable gate arrays using resistivity sensitive memories
View Patent ↗Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals. The memory can be vertically configured in one or more memory planes that are vertically stacked upon each other and are positioned above a logic plane.
1. An integrated circuit for a field programmable gate array, comprising:
a substrate including active circuitry fabricated in a logic plane and an inter-layer interconnect structure; and
at least one memory plane in contact with the substrate and vertically positioned over the substrate, the at least one memory plane including a plurality of non-volatile two-terminal memory elements configured in a two-terminal cross-point array, the inter-layer interconnect structure operative to electrically couple the active circuitry with the plurality of non-volatile two-terminal memory elements, and
wherein the active circuitry includes sequencer logic operative to provide sequential memory addresses and write data for data operations on the plurality of non-volatile two-terminal memory elements, interface logic operative to receive the write data, memory logic operative to access the plurality of non-volatile two-terminal memory elements for the data operations, and configurable logic electrically coupled with at least a portion of the plurality of non-volatile two-terminal memory elements and operative to form a plurality of programmable cells configured to implement a programmed logic function.
2. The integrated circuit of claim 1 , wherein each non-volatile two-terminal memory element stores data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across terminals of the non-volatile two-terminal memory element and new data can be written by applying a write voltage across terminals of the non-volatile two-terminal memory element.
3. The integrated circuit of claim 1 , wherein each non-volatile two-terminal memory element includes an electrolytic tunnel barrier and a mixed valence conductive oxide.
4. The integrated circuit of claim 1 , wherein at least a portion of the plurality of non-volatile two-terminal memory elements in the at least one memory plane are configured as boot memory.
5. The integrated circuit of claim 4 , wherein the boot memory includes at least one look-up table configured to store data operative to initialize non-volatile two-terminal memory elements that are un-programmed.
6. The integrated circuit of claim 1 , wherein the active circuitry comprises CMOS circuitry.
7. The integrated circuit of claim 1 , wherein a write operation on any of the plurality of non-volatile two-terminal memory elements does not require an erase operation prior to the write operation.
8. An integrated circuit for a field programmable gate array, comprising:
a substrate including active circuitry fabricated in a logic plane and an inter-layer interconnect structure; and
at least one memory plane in contact with the substrate and vertically positioned over the substrate, the at least one memory plane including a plurality of cell memories, each cell memory including a plurality of non-volatile two-terminal memory elements configured in a two-terminal cross-point array, the inter-layer interconnect structure operative to electrically couple the active circuitry with the plurality of non-volatile two-terminal memory elements,
wherein the active circuitry includes a plurality of memory logics, each memory logic operative to individually access a specific one of the plurality of cell memories for data operations, and
wherein the active circuitry further includes sequencer logic operative to provide sequential memory addresses and write data for the data operations on the plurality of cell memories, interface logic operative to receive the write data, and configurable logic electrically coupled with at the plurality of cell memories and operative to form a plurality of programmable cells configured to implement a programmed logic function.