Programmable logic device structure using third dimensional memory

1. A method for programming a Programmable Logic Device (PLD) comprising:

providing a substrate including a logic layer having active circuitry fabricated on the substrate and at least one layer of third dimensional memory fabricated in contact with and directly above the substrate, the at least one layer of third dimensional memory in electrical communication with the active circuitry;

selecting an input signal from a plurality of inputs that are electrically coupled with the active circuitry;

maintaining routing data independent of the application of electrical power to the at least one layer of third dimensional memory by storing the routing data in at least one non-volatile register, each non-volatile register including at least one non-volatile memory element positioned in the at least one layer of third dimensional memory and non-volatile register logic included in the active circuitry and electrically coupled with the at least one non-volatile memory element; and

routing the input signal to a routing line.

2. The method of claim 1 and further comprising:

testing a routing path formed from an input at which the input signal is applied via the routing line to at least one logic gate positioned in the active circuitry.

3. The method of claim 2 and further comprising:

writing different routing data into the at least one layer of third dimensional memory to alter the routing path to form a different routing path; and

testing the different routing path formed from the input at which the input signal is applied to at least one other logic gate positioned in the active circuitry.

4. The method of claim 2 and further comprising:

clearing the different routing data.

5. The method of claim 2 , wherein the writing and the testing occur dynamically.

6. The method of claim 1 , wherein the at least one non-volatile memory element comprises at least one two-terminal memory element configured in a two-terminal cross-point memory array.

7. The method of claim 6 , wherein each two-terminal memory element is operative to store data as a plurality of conductivity profiles and is configured to retain stored data in the absence of electrical power, stored data is non-destructively determined by applying a read voltage across the two-terminal memory element, and new data is written by applying a write voltage across the two-terminal memory element.

8. The method of claim 6 , wherein each two-terminal memory element includes an electrolytic tunnel barrier and a mixed valence conductive oxide.

9. The method of claim 1 , wherein the at least one layer of third dimensional memory comprises a plurality of vertically stacked memory layers.

10. The method of claim 1 , wherein the at least one layer of third dimensional memory and the active circuitry are configured to implement a programmable array logic (PAL).

11. The method of claim 1 , wherein the at least one layer of third dimensional memory and the active circuitry are configured to implement a gate array.

12. The method of claim 1 , wherein the at least one layer of third dimensional memory and the active circuitry are configured to implement a field programmable gate array (FPGA).

13. The method of claim 1 , wherein the active circuitry comprises CMOS circuitry.

14. A method for programming a Programmable Logic Device (PLD) comprising:

providing active circuitry fabricated on a logic layer of a substrate, the logic layer including a plurality of inputs, a plurality of outputs, logic elements, and logic configuration circuitry operative to use routing data to configure the logic elements, the logic elements when configured, are operative to generate at least one output on at least one of the plurality of outputs in response to at least one signal on at least one of the plurality of inputs;

providing at least one layer of third dimensional memory fabricated in contact with and directly above the substrate, the at least one layer of third dimensional memory including a plurality of non-volatile memory cells operative to store the routing data, the plurality of non-volatile memory cells are in electrical communication with the active circuitry;

selecting the at least one signal from the plurality of inputs that are electrically coupled with the active circuitry;

maintaining the routing data independent of the application of electrical power to the plurality of non-volatile memory cells; and

routing the at least one signal to at least one of the plurality of output signals.

15. The method of claim 14 , wherein each non-volatile memory cell is configured in a two-terminal cross-point memory array.

16. The method of claim 15 , wherein each non-volatile memory cell includes a two-terminal memory element operative to store data as a plurality of conductivity profiles and is configured to retain stored data in the absence of electrical power, stored data is non-destructively determined by applying a read voltage across the two-terminal memory element, and new data is written by applying a write voltage across the two-terminal memory element.

17. The method of claim 16 , wherein each two-terminal memory element includes an electrolytic tunnel barrier and a mixed valence conductive oxide.

18. The method of claim 14 , wherein the at least one layer of third dimensional memory comprises a plurality of vertically stacked memory layers.

19. The method of claim 14 , wherein the active circuitry comprises CMOS circuitry.

20. The method of claim 14 and further comprising:

testing a routing path formed from one of the plurality of inputs at which the at least one signal is applied via a routing line to at least one logic gate positioned in the logic elements.