IP Library Granted Patent US 8,248,159
Granted Patent B2
US 8,248,159 · App. 12/658,498 · Granted Aug 21, 2012

Model based distortion reduction for power amplifiers

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Quick Facts
Patent No.
US 8,248,159
App. No.
12/658,498
Granted
Aug 21, 2012
Kind
B2
Abstract

A method of processing a signal is disclosed. The method comprises generating a digital signal, converting the digital signal to an analog signal, and generating an amplified analog signal having distortions. The method further comprises converting the amplified analog signal to a feedback digital signal at a sample rate and updating a model of the distortions based on the feedback digital signal.

Claims (22)

1. A method of processing a signal comprising:

generating a digital signal, wherein generating comprising compensating for distortions, wherein compensating for the distortions comprise processing the digital signal using a model to create a predicted distorted digital signal and subtracting the predicted distorted digital signal from the digital signal to create a precompensated digital signal;

converting the precompensated digital signal to an analog signal;

generating an amplified analog signal having distortions, wherein the distortions in the amplified analog output signal are reduced;

converting the amplified analog signal to a feedback digital signal at a sample rate; and

updating a model of the distortions based on the feedback digital signal, wherein updating the model is calculating the model based on an error signal, wherein the error signal is derived from the difference between 1) a model processed feedback digital signal and 2) the difference between the precompensated digital signal and the feedback digital signal.

2. A method as in claim 1 , further including upshifting the digital signal before converting to the analog signal and downshifting before converting the amplified analog signal to the feedback digital signal.

3. A method as in claim 1 , further including upshifting the analog signal before generating the amplified analog signal and downshifting before converting the amplified analog signal to the feedback digital signal.

4. A method as in claim 1 , wherein the model includes memory effects.

5. A method as in claim 1 , wherein updating the model occurs at a selectable rate.

6. A method as in claim 1 , wherein the distortions in the amplified analog output signal are reduced for frequencies higher than half the sample rate of the feedback digital signal.

7. A system for processing a signal comprising:

a generator of a digital signal, wherein the generator compensates for distortions, wherein compensating for the distortions is processing the digital signal using a model to create a predicted distorted digital signal and subtracting the predicted distorted digital signal from the digital signal to create a precompensated digital signal;

a first converter for converting the precompensated digital signal to an analog signal;

an amplifier for generating an amplified analog signal having distortions, wherein the distortions in the amplified analog output signal are reduced;

a second converter for converting the amplified analog signal to a feedback digital signal at a sample rate; and

an updater for updating the model of the distortions based on the feedback digital signal, wherein updating the model is calculating the model based on an error signal, wherein the error signal is derived from the difference between 1) a model processed feedback digital signal and 2) the difference between the precompensated digital signal and the feedback digital signal.

8. A system as in claim 7 , further including an upshifter for upshifting the digital signal before converting to the analog signal and downshifting before converting the amplified analog signal to the feedback digital signal.

9. A system as in claim 7 , further including an upshifter for upshifting the analog signal before generating the amplified analog signal and downshifting before converting the amplified analog signal to the feedback digital signal.

10. A system as in claim 7 , wherein the model includes memory effects.

11. A system as in claim 7 , wherein updating the model occurs at a selectable rate.

12. A system as in claim 7 , wherein the distortions in the amplified analog output signal are reduced for frequencies higher than half the sample rate of the feedback digital signal.

Assignments (7)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
CHANGE OF NAME Recorded Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: OPTICHRON, INC.
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 026592/0811 →
SECURITY AGREEMENT Recorded Dec 1, 2010
From: OPTICHRON, INC.
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 025434/0718 →