IP Library Granted Patent US 7,984,223
Granted Patent B2
US 7,984,223 · App. 12/659,545 · Granted Jul 19, 2011

Information device including main processing circuit, interface circuit, and microcomputer

Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 7,984,223
App. No.
12/659,545
Granted
Jul 19, 2011
Kind
B2
Abstract

An information device packaged in one package includes a main function unit and an interface function unit. The main function unit includes a main processing circuit for executing signal processing related to a main function in the information device and a first microcomputer for controlling the main processing circuit by executing a first firmware program. The interface function unit includes an interface function unit including a first interface circuit for receiving data from an exterior device located outside of the information device to provide to the main function unit, a second interface circuit for performing an authentication operation with the exterior device, a second microcomputer for controlling the first interface circuit, and a memory for storing a second firmware program for controlling the first interface circuit.

Claims (18)

1. An information device packaged in one package, comprising:

a main function unit including a main processing circuit for executing signal processing related to a main function in said information device and a first microcomputer for controlling said main processing circuit by executing a first firmware program; and

an interface function unit including a first interface circuit for receiving data from an exterior device located outside of said information device to provide to said main function unit, a second interface circuit for performing an authentication operation with the exterior device, a second microcomputer for controlling said first interface circuit, and a memory for storing a second firmware program for controlling said first interface circuit,

wherein said second microcomputer downloads said second firmware from said memory by executing a download program, and controlling said authentication operation of said second interface circuit,

wherein said interface function unit is subjected to a single-chip process separately from said main function unit,

wherein said first interface circuit and said second microcomputer are connected to each other by using a parallel interface, and

wherein said first interface circuit is an interface circuit conforming to HDMI (High-Definition Multimedia Interface).

2. The information device according to claim 1 ,

wherein said first interface circuit receives an externally input video signal and an externally input audio signal corresponding to said video signal to output said video signal and said audio signal in parallel, said information device further comprising a lip-sync circuit for adjusting the timing between said video signal and said audio signal output in parallel from said first interface circuit, said lip-sync circuit being subjected to the single-chip process together with said first interface circuit and said second microcomputer.

3. The information device according to claim 1 ,

wherein said first interface circuit includes a receiver circuit for receiving an external signal to output said external signal, and a transmitter circuit for outputting a signal output from said receiver circuit to the outside of said information device.

4. The information device according to claim 1 ,

wherein said second microcomputer has the function of communicating with said first microcomputer.

5. The information device according to claim 1 , further comprising:

a plurality of input ports for receiving respective external signals; and

a switch circuit for selecting one of the external signals input to said plurality of input ports to output a selected signal to said first interface circuit, said switch circuit being subjected to the single-chip process together with said first interface circuit and said second microcomputer.

6. The information device according to claim 1 ,

wherein said first interface circuit receives an encrypted signal input from the outside of said information device, decrypts said encrypted signal, and outputs the decrypted signal, said information device further comprising a watermarking circuit for embedding a watermark into a signal output from said first interface circuit to output the resultant signal, said watermarking circuit being subjected to the single-chip process together with said first interface circuit and said second microcomputer.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
MERGER Recorded Aug 27, 2010
From: RENESAS TECHNOLOGY CORPORATION
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024892/0877 →
CHANGE OF NAME Recorded Aug 27, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024944/0437 →
Priority Claims (1)
JP 2005-310939 · Oct 26, 2005 · national
Continuity (2)
Continuation 11584550 · Oct 23, 2006
Related Publication 20100191883A1 · Jul 29, 2010