Output circuit using analog amplifier

1. An output circuit comprising:

an analog amplifier circuit which comprises:

a differential amplifier stage configured to receive an input voltage, and

first to n th output systems (n is a natural number more than 1);

first to n th output nodes;

an output pad; and

first to n th electrostatic protection resistances,

wherein an i th output system (i is a natural number between 2 and n) of said first to n th output systems comprises:

an i th PMOS transistor having a drain connected with said i th output node of said first to n th output nodes and a gate connected with a first output of said differential amplifier stage; and

an i th NMOS transistor having a drain connected with said i th output node and a gate connected with a second output of said differential amplifier stage, and

wherein said first to n th electrostatic protection resistances are respectively connected between said first to n th output nodes and said output pad.

2. The output circuit according to claim 1 , further comprising:

first to n th feedback resistances,

wherein said differential amplifier stage comprises a non-inversion input terminal configured to receive the input voltage and an inversion input terminal, and

wherein said first to n th feedback resistances are respectively connected between said first to n th output nodes and said inversion input terminal.

3. The output circuit according to claim 1 , further comprising:

first to n th P-side phase compensation capacitances; and

first to n th N-side phase compensation capacitances,

wherein respective one ends of said first to n th P-side phase compensation capacitances are respectively connected with said first to n th output nodes, and respective one ends of said first to n th N-side phase compensation capacitances are respectively connected with said first to n th output nodes, and

wherein the other ends of an i th P-side compensation capacitance of said first to n th P-side phase compensation capacitances and an i th N-side compensation capacitance of said first to n th P-side phase compensation capacitances are respectively connected with said first and second outputs of said differential amplifier stage.

4. The output circuit according to claim 1 , further comprising:

a (n+1) th electrostatic protection resistance,

wherein said differential amplifier stage comprises a non-inversion input terminal configured to receive the input voltage and an inversion input terminal, and

wherein said (n+1) th electrostatic protection resistances is connected between said output pad and said inversion input terminal.

5. The output circuit according to claim 1 , wherein the resistance values of the said first to n th electrostatic protection resistances are substantially the same.

6. The output circuit according to claim 1 , further comprising:

first to n th feedback resistances,

wherein said first to n th feedback resistances are respectively connected between said first to n th output nodes and an inversion input terminal of said differential amplifier stage, and

wherein a voltage at a common connection point of the feedback resistances and an input voltage of the non-inversion input terminal are equal to each other.

7. The output circuit according to claim 1 , further comprising:

first to n th feedback resistances,

wherein said first to n th feedback resistances are respectively connected between said first to n th output nodes and an inversion input terminal of said differential amplifier stage.

8. The output circuit according to claim 1 , further comprising:

first to n th P-side phase compensation capacitances; and

first to n th N-side phase compensation capacitances.

9. The output circuit according to claim 1 , further comprising:

first to n th P-side phase compensation capacitances; and

first to n th N-side phase compensation capacitances,

wherein respective one ends of said first to n th P-side phase compensation capacitances are respectively connected with said first to n th output nodes, and respective one ends of said first to n th N-side phase compensation capacitances are respectively connected with said first to n th output nodes.

10. The output circuit according to claim 1 , further comprising:

a (n+1) th electrostatic protection resistance,

wherein said (n+1) th electrostatic protection resistance is connected between said output pad and an inversion input terminal of said differential amplifier stage.

11. An output circuit comprising:

an analog amplifier circuit which comprises:

a differential amplifier stage configured to receive an input voltage, and

first to n th output systems (n is a natural number more than 1);

first to n th output nodes;

an output pad;

first to n th electrostatic protection resistances,

wherein an i th output system (i is a natural number between 2 and n) of said first to n th output systems comprises:

an i th PMOS transistor having a drain connected with said i th output node of said first to n th output nodes and a gate connected with a first output of said differential amplifier stage; and

an i th NMOS transistor having a drain connected with said i th output node and a gate connected with a second output of said differential amplifier stage, and

wherein said first to n th electrostatic protection resistances are respectively connected between said first to n th output nodes and said output pad; and

first to n th feedback resistances are respectively connected between said first to n th output nodes and an input terminal of the differential amplifier stage.

12. The output circuit according to claim 11 , wherein said first to n th feedback resistances are respectively connected between said first to n th output nodes and the input terminal comprising an inversion input terminal.

13. The output circuit according to claim 11 , further comprising:

first to n th P-side phase compensation capacitances; and

first to n th N-side phase compensation capacitances.

14. The output circuit according to claim 13 , wherein respective one ends of said first to n th P-side phase compensation capacitances are respectively connected with said first to n th output nodes, and respective one ends of said first to n th N-side phase compensation capacitances are respectively connected with said first to n th output nodes.

15. The output circuit according to claim 14 , wherein the other ends of an i th P-side compensation capacitance of said first to n th P-side phase compensation capacitances and an i th N-side compensation capacitance of said first to n th P-side phase compensation capacitances are respectively connected with said first and second outputs of said differential amplifier stage.

16. The output circuit according to claim 11 , further comprising a (n+1) th electrostatic protection resistance.

17. The output circuit according to claim 16 , wherein said differential amplifier stage comprises a non-inversion input terminal configured to receive the input voltage and an inversion input terminal.

18. The output circuit according to claim 16 , wherein said (n+1) th electrostatic protection resistance is connected between said output pad and said inversion input terminal.