IP Library Granted Patent US 8,570,313
Granted Patent B2
US 8,570,313 · App. 12/662,627 · Granted Oct 29, 2013

Display panel driver

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,570,313
App. No.
12/662,627
Granted
Oct 29, 2013
Kind
B2
Abstract

A display panel driver is provided with: first and second amplifiers; first to n-th even output nodes, n being an integer of two or more; first to n-th odd output nodes; first and second output pads connected to data lines of a display panel, respectively; first to n-th switch blocks; first to n-th even electrostatic protection resistors; and first to n-th odd electrostatic protection resistors. The i-th switch block out of the first to n-th switch blocks is configured to switch connections between the first and second amplifiers and i-th even and odd electrostatic protection resistors out of the first to n-th even and odd electrostatic protection resistors. The first to n-th even electrostatic protection resistors are connected between the first to n-th even output nodes and the first output pad, respectively. The first to n-th odd electrostatic protection resistors are connected between the first to n-th odd output nodes and the second output pad, respectively.

Claims (31)

1. A display panel driver, comprising:

first and second amplifiers;

first to n-th even output nodes, n being an integer of two or more;

first to n-th odd output nodes;

first and second output pads connected to data lines of a display panel, respectively;

first to n-th switch blocks;

first to n-th even electrostatic protection resistors; and

first to n-th odd electrostatic protection resistors,

wherein an i-th switch block out of said first to n-th switch blocks is configured to switch connections between said first and second amplifiers and i-th even and odd electrostatic protection resistors out of said first to n-th even and odd electrostatic protection resistors,

wherein said first to n-th even electrostatic protection resistors are connected between said first to n-th even output nodes and said first output pad, respectively, and

wherein said first to n-th odd electrostatic protection resistors are connected between said first to n-th odd output nodes and said second output pad, respectively.

2. The display panel driver according to claim 1 , wherein said first amplifier is configured to generate a drive voltage lower than a common voltage fed to an opposite electrode of said display panel;

wherein said second amplifier is configured to generate a drive voltage higher than said common voltage;

wherein said i-th switch block includes:

a first switch connected between said first amplifier and said i-th even output node;

a second switch connected between said second amplifier and said i-th odd output node;

a third switch connected between said first amplifier and said i-th odd output node; and

a fourth switch connected between said second amplifier and said i-th even output node.

3. The display panel driver according to claim 1 , further comprising:

first to n-th charge collecting switch blocks; and

a common line,

wherein an i-th charge collecting switch block out of said first to n-th charge collecting switch blocks includes:

a fifth switch connected between said i-th even output node and said i-th odd output node;

a sixth switch connected between said i-th odd output node and said common line; and

a seventh switch connected between said i-th even output node and said common line.

4. The display panel driver according to claim 1 , further comprising a cross switch block connected between said first and second amplifiers and first and second D/A converters,

wherein said first and second amplifiers each provide a rail-to-rail operation,

wherein said cross switch block is configured to switch connections between outputs of said first and second D/A converters and inputs of said first and second amplifiers, and

wherein said i-th switch block includes:

a first switch connected between said first amplifier and said i-th even output node; and

a second switch connected between said second amplifier and said i-th odd output node.

Assignments (3)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
CHANGE OF NAME Recorded Oct 26, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025813/0759 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2010
From: NISHIMURA, KOUICHI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 024585/0175 →