Image signal processing device
An image signal processing device 1 comprises a delay part 10 , a basic correction value output part 20 , and a corrected image data output part 30 . To the basic correction value output part 20 , data G 1 [7:4] of high order 4 bits of image data G 1 [7:0] of a first frame to be output from the delay part 10 is input and data G 2 [7:4] of high order 4 bits of image data G 2 [7:0] of a second frame to be input to the delay part 10 is input, and the basic correction value output part 20 outputs basic correction values D 1 to D 4 corresponding to the data. To the corrected image data output part 30 , G 1 [7:0], G 2 [7:0] and D 1 to D 4 are input, and the corrected image data output part 30 performs when “G 1 [7:4]=G 2 [7:4]” holds and performs different processing when “G 1 [7:4]≠G 2 [7:4]” holds, and acquires corrected image data G 2 ′[7:0] corresponding to data (G 1 [7:0], G 2 [7:0]) by interpolation calculation.
1. An image signal processing device that outputs an image signal to a liquid crystal display device after processing image data of each frame of the image signal, comprising:
a delay part to which image data of each frame of the image signal is input, and which outputs the image data after delaying the image data by a period of time corresponding to one frame;
a basic correction value output part:
to which:
data G 1 [n−1:k] of high order (n−k) bits of image data G 1 [n−1:0] of n bits of a first frame to be output from the delay part, where n is an integer equal to or greater than four and k an integer equal to or greater than two and equal to or less than (n−2); and
data G 2 [n−1:k] of high order (n−k) bits of image data G 2 [n−1:0] of n bits of a second frame to be input to the delay part are input; and
which outputs:
a basic correction value D 1 corresponding to data (G 1 [n−1:k], G 2 [n−1:k]);
a basic correction value D 2 corresponding to data (G 1 [n−1:k], G 2 [n−1:k]+1);
a basic correction value D 3 corresponding to data (G 1 [n−1:k]+1, G 2 [n−1:k]); and
a basic correction value D 4 corresponding to data (G 1 [n−1:k]+1, G 2 [n−1:k]+1); and
a corrected image data output part:
to which:
the image data G 1 [n−1:0] of n bits of the first frame to be output from the delay part;
the image data G 2 [n−1:0] of n bits of the second frame to be input to the delay part; and
basic correction values D 1 to D 4 output from the basic correction value output part are input; and
which acquires corrected image data corresponding to data (G 1 [n:0], G 2 [n:0]) by interpolation calculation and outputs the corrected image data thus acquired to the liquid crystal display device, wherein
the corrected image data output part acquires, when “G 1 [n−1:k]=G 2 [n−1:k]” holds for the high order (n−k) bits of the image data:
the corrected image data by interpolation calculation based on the basic correction values D 1 , D 2 and D 4 when “G 1 [k−1:0]<G 2 [k−1:0]” holds for the low order k bits of the image data;
the corrected image data by interpolation calculation based on the basic correction values D 1 , D 3 and D 4 when “G 1 [k−1:0]≧G 2 [k−1:0]” holds for the low order k bits of the image data; and
the corrected image data by bilinear interpolation calculation based on the basic correction values D 1 to D 4 when “G 1 [n−1:k]≠G 2 [n−1:k]” holds for the high order (n−k) bits of the image data.
2. The image signal processing device according to claim 1 , wherein
the corrected image data output part acquires, when “G 1 [n−1:k]=G 2 [n−1:k]” holds, the corrected image data by bilinear interpolation calculation based on the basic correction value D 1 to D 4 by:
taking a value obtained by an expression “D 3 =D 1 +D 4 −D 2 ” as the basic correction value D 3 when “G 1 [k−1:0]<G 2 [k−1:0]” holds for the low order k bits of the image data; and
taking a value obtained by an expression “D 2 =D 1 +D 4 −D 3 ” as the basic correction value D 2 when “G 1 [k−1:0]≧G 2 [k−1:0]” holds for the low order k bits of the image data.