Semiconductor integrated circuit device
View Patent ↗The present invention provides a semiconductor integrated circuit device in which characteristics of an SOI transistor are effectively used to achieve higher speed, higher degree of integration, and also reduction in voltage and power consumption. The semiconductor integrated circuit device according to the present invention has a configuration in which a plurality of external power supply lines and body voltage control lines are alternately arranged in one direction so as to extend over the entire chip, which supply power and a body voltage to logic circuits, an analog circuit and memory circuits. A body voltage control type logic gate is fully applied in the logic circuit, whereas the body voltage control type logic gate is partially applied in the memory circuit.
1. A semiconductor integrated circuit device comprising a plurality of logic gates, wherein:
each of said plurality of logic gates includes MOS transistors, the MOS transistors having, in accordance with a power supply voltage, two states of a partially-depleted state in which a region which is not depleted remains in a channel region and a fully-depleted state in which said channel region is fully depleted;
said MOS transistors are configured so that a body including said channel region is electrically separated from a semiconductor substrate and a potential of said body is set to an appropriate potential; and
said body is applied with a positive body voltage in said partially-depleted state so that an operating speed in a case where first power supply voltages indicating said partially-depleted state are supplied is equal to an operating speed in a case where a second power supply voltage indicating said fully-depleted state is supplied.
2. The semiconductor integrated circuit device according to claim 1 , wherein:
said MOS transistors are formed on an SOI substrate including said semiconductor substrate, a buried oxide film disposed on said semiconductor substrate, and an SOI layer disposed on said buried oxide film; and
said body is formed within a surface of said SOI layer, a periphery thereof being surrounded by an isolation insulating film.
3. The semiconductor integrated circuit device according to claim 2 , wherein said body of said MOS transistor is applied with, as said body voltage, a voltage higher than a ground potential in a case of an N-channel MOS transistor and a voltage lower than said power supply voltage in a case of a P-channel MOS transistor.
4. The semiconductor integrated circuit device according to claim 1 , wherein a delay amount of each of said plurality of logic gates changes discontinuously at said power supply voltage becoming a border between said partially-depleted state and said fully-depleted state of said MOS transistor.
5. The semiconductor integrated circuit device according to claim 2 , wherein said body and a gate of said MOS transistor are electrically connected to each other.
6. The semiconductor integrated circuit device according to claim 1 , wherein:
said first power supply voltages are supplied from an outside;
said second power supply voltage is generated in said semiconductor integrated circuit device by an internal voltage generating circuit; and
said internal voltage generating circuit includes:
a first ring oscillator driven by said first power supply voltage and composed of said MOS transistors;
a second ring oscillator driven by said second power supply voltage and composed of said MOS transistors;
a phase comparator comparing phases of first and second frequencies at which said first and second ring oscillators oscillate, respectively; and
a correction circuit correcting, based on a comparison result by said phase comparator, said second power supply voltage supplied to said second ring oscillator so that said second frequency is equal to said first frequency.
7. The semiconductor integrated circuit device according to claim 1 , wherein:
said first and second power supply voltages are supplied from an outside;
said body voltage applied to said body of said MOS transistor is generated in said semiconductor integrated circuit device by an internal voltage generating circuit; and
said internal voltage generating circuit includes:
a first ring oscillator driven by said first power supply voltage and composed of said MOS transistors;
a second ring oscillator driven by said second power supply voltage and composed of said MOS transistors;
a phase comparator comparing phases of first and second frequencies at which said first and second ring oscillators oscillate, respectively; and
a correction circuit correcting, based on a comparison result by said phase comparator, said body voltage applied to said body of said MOS transistors constituting said second ring oscillator so that said second frequency is equal to said first frequency.
8. The semiconductor integrated circuit device according to claim 6 , wherein:
said semiconductor integrated circuit device includes:
a first semiconductor integrated circuit;
second semiconductor integrated circuits; and
a self-correcting power source outputting said second power supply voltage with said first power supply voltage supplied from said outside being as an operating voltage;
said self-correcting power source includes said internal voltage generating circuit and outputs said second power supply voltage corrected by said correction circuit;
said first semiconductor integrated circuit includes said plurality of logic gates, is supplied with said first power supply voltage during normal operation of said semiconductor integrated circuit device, and is supplied with said second power supply voltage lower than said first power supply voltage during stand-by of said semiconductor integrated circuit device;
said second semiconductor integrated circuit is supplied with said first power supply voltage during normal operation of said semiconductor integrated circuit device, and supply of said first power supply voltages is interrupted during stand-by of said semiconductor integrated circuit device;
said first and second semiconductor integrated circuits and said self-correcting power source are formed on a common SOI substrate including said semiconductor substrate, a buried oxide film disposed on said semiconductor substrate, and an SOI layer disposed on said buried oxide film; and
said body is formed within a surface of said SOI layer, a periphery thereof being surrounded by an isolation insulating film.
9. A semiconductor integrated circuit device, comprising:
a first semiconductor integrated circuit;
second semiconductor integrated circuits; and
a power source outputting a second power supply voltage with a first power supply voltage supplied from an outside being as an operating voltage, wherein:
said first semiconductor integrated circuit is supplied with said first power supply voltage during normal operation of said semiconductor integrated circuit device, and is supplied with said second power supply voltage lower than said first power supply voltage during stand-by of said semiconductor integrated circuit device;
said second semiconductor integrated circuit is supplied with said first power supply voltage during normal operation of said semiconductor integrated circuit device, and supply of said first power supply voltage is interrupted during stand-by of said semiconductor integrated circuit device;
said first semiconductor integrated circuit and said power source comprise a plurality of logic gates including MOS transistors having, in accordance with a power supply voltage, two states of a partially-depleted state in which a region which is not depleted remains in a channel region and a fully-depleted state in which said channel region is fully depleted;
said MOS transistors are configured so that a body including said channel region is electrically separated from a semiconductor substrate and a potential of said body is set to an appropriate potential;
said body is applied with a positive body voltage in said partially-depleted state so that an operating speed in a case where said first power supply voltage indicating said partially-depleted state is supplied is equal to an operating speed in a case where said second power supply voltage indicating said fully-depleted state is supplied;
said first and second semiconductor integrated circuits and said power source are formed on a common SOI substrate including a semiconductor substrate, a buried oxide film disposed on said semiconductor substrate, and an SOI layer disposed on said buried oxide film; and
said body is formed within a surface of said SOI layer, a periphery thereof being surrounded by an isolation insulating film.