Semiconductor device where logic region and DRAM are formed on same substrate

1. A semiconductor device having a DRAM region and a logic region embedded therein, comprising:

a substrate having said DRAM region and said logic region respectively formed thereon;

a first transistor formed in said DRAM region, and having a first gate insulating film; and

a second transistor formed in said logic region, and having a second gate insulating film,

wherein equivalent oxide thickness T 1 of said first gate insulating film of said first transistor is not larger than equivalent oxide thickness T 2 of said second gate insulating film of said second transistor,

said second transistor formed in said logic region has, at each end of the source/drain regions thereof, a pocket region which contains an impurity ion having a conductivity type different from a conductivity type of an impurity ion composing said source/drain regions, said first transistor formed in said DRAM region has no pocket region formed at each end of the source/drain regions thereof, and

at least a part of said pocket region is located in surficial portions of said substrate between the source/drain regions.

2. The semiconductor device as claimed in claim 1 ,

wherein said first transistor is configured to be applied with a negative bias voltage in the standby period.

3. The semiconductor device as claimed in claim 2 ,

wherein said second transistor is configured to be applied with zero voltage in the standby period.

4. The semiconductor device as claimed in claim 1 ,

wherein said source/drain regions of said second transistor formed in said logic region, and said source/drain regions of said first transistor formed in said DRAM region have silicide layers respectively formed in the surficial portions thereof.

5. A semiconductor device having a DRAM region and a logic region embedded therein, comprising:

a substrate having said DRAM region and said logic region respectively formed thereon;

a first transistor formed in said DRAM region, and having a first gate insulating film; and

a second transistor formed in said logic region, and having a second gate insulating film,

wherein equivalent oxide thickness T 1 of said first gate insulating film of said first transistor is smaller than 2.2 nm,

said second transistor formed in said logic region has, at each end of the source/drain regions thereof, a pocket region which contains an impurity ion having a conductivity type different from a conductivity type of an impurity ion composing said source/drain regions,

said first transistor formed in said DRAM region has no pocket region formed at each end of the source/drain regions thereof, and

at least a part of said pocket region is located in surficial portions of said substrate between the source/drain regions.

6. The semiconductor device as claimed in claim 5 ,

wherein said first transistor is configured to be applied with a negative bias voltage in the standby period.

7. The semiconductor device as claimed in claim 6 ,

wherein said second transistor is configured to be applied with zero voltage in the standby period.

8. The semiconductor device as claimed in claim 5 ,

wherein said source/drain regions of said second transistor formed in said logic region, and said source/drain regions of said first transistor formed in said DRAM region have silicide layers respectively formed in the surficial portions thereof.

9. A semiconductor device having a DRAM region and a logic region embedded therein, comprising:

a substrate having said DRAM region and said logic region respectively formed thereon;

a first transistor formed in said DRAM region, and having a first gate insulating film and a first gate electrode;

a second transistor formed in said logic region, and having a second gate insulating film and a second gate electrode; and

a negative bias generating circuit applying a negative bias voltage to said first gate electrode,

wherein equivalent oxide thickness T 1 of said first gate insulating film of said first transistor is thinner than equivalent oxide thickness T 2 of said second gate insulating film of said second transistor,

said negative bias generating circuit applies a negative bias voltage to said first gate electrode in the standby period, and

a dose of impurity ion implanted into a channel region in said DRAM region is lower than a dose of impurity ion implanted into a channel region in said logic region.

10. The semiconductor device as claimed in claim 9 ,

wherein said second transistor is configured to be applied with zero voltage in the standby period.

11. The semiconductor device as claimed in claim 9 ,

wherein said source/drain regions of said second transistor formed in said logic region, and said source/drain regions of said first transistor formed in said DRAM region have silicide layers respectively formed in the surficial portions thereof.

12. A semiconductor device having a DRAM region and a logic region embedded therein, comprising:

a substrate having said DRAM region and said logic region respectively formed thereon;

a first transistor formed in said DRAM region, and having a first gate insulating film and a first gate electrode;

a second transistor formed in said logic region, and having a second gate insulating film and a second gate electrode; and

a negative bias generating circuit applying a negative bias voltage to said first gate electrode,

wherein equivalent oxide thickness T 1 of said first gate insulating film of said first transistor is smaller than 2.2 nm,

said negative bias generating circuit applies a negative bias voltage to said first gate electrode in the standby period,

the equivalent oxide thickness T 1 of said first gate insulating film of said first transistor is thinner than the equivalent oxide thickness T 2 of said second gate insulating film of said second transistor, and

a dose of impurity ion implanted into a channel region in said DRAM region is lower than a dose of impurity ion implanted into a channel region in said logic region.

13. The semiconductor device as claimed in claim 12 ,

wherein said second transistor is configured to be applied with zero voltage in the standby period.

14. The semiconductor device as claimed in claim 12 ,

wherein said source/drain regions of said second transistor formed in said logic region, and said source/drain regions of said first transistor formed in said DRAM region have silicide layers respectively formed in the surficial portions thereof.