Three dimensional integration with through silicon vias having multiple diameters
A method is disclosed which includes patterning a photoresist layer on a substrate of a structure, removing a first portion of the photoresist layer to expose a first area of the substrate, etching the first area to form a cavity having a first depth, removing a second portion of the photoresist to expose an additional area of the substrate, and etching the cavity to expose a first conductor in the structure and the additional area to expose a second conductor in the structure.
1. A method comprising:
patterning a photoresist layer on a substrate of a structure having at least one conductor embedded therein;
removing a first portion of the photoresist layer to expose a first area of the substrate;
etching the first area to form a cavity having a first depth;
removing a second portion of the photoresist to expose an additional area of the substrate; and
etching the cavity to expose a first conductor in the structure and the additional area to expose a second conductor in the structure.
2. The method of claim 1 , wherein the structure includes a first wafer component arranged on a second wafer component.
3. The method of claim 2 , wherein first wafer component has a substrate portion and a wiring level portion arranged on a wiring level portion of second wafer component.
4. The method of claim 3 , wherein the wiring level portion of the first wafer component and the wiring level portion of the second wafer component are bonded together with an adhesive.
5. The method of claim 3 , wherein the wiring level portion of the first wafer component and the wiring level portion of the second wafer component are bonded together with a metal.
6. The method of claim 1 , wherein the structure includes a first chip component arranged on a second chip component.
7. The method of claim 1 , wherein the substrate includes a silicon material.
8. The method of claim 1 , wherein the removal of the second portion of the photoresist layer to expose an additional area of the substrate is performed in-situ.
9. The method of claim 1 , wherein the photoresist layer is patterned on an exposed silicon surface of the structure.
10. The method of claim 1 , wherein after etching the cavity to expose a first conductor in the structure and the additional area to expose a second conductor in the structure the method further comprises:
forming a dielectric layer in the cavity;
removing a portion of the dielectric layer;
depositing a barrier layer on the dielectric;
filling the cavity with a conductive material; and
removing the excess conductive material by planarization.
11. The method of claim 10 , wherein the conductive material is operative to electrically connect the first conductor and the second conductor.