Systems and methods for on-chip power management
A power measurement system is disclosed for use on an integrated circuit for measuring the power used by the integrated circuit. The power measurement system includes a low-dropout voltage regulator and a signal input unit. The low-dropout voltage regulator includes a power transistor that couples a supply voltage to a circuit to be powered by the supply voltage, and the low-dropout voltage regulator provides an internal adjustment signal (V sen ) for adjusting the internal resistance of the power transistor. The signal input unit receives the internal adjustment signal (V sen ) and provides a power measurement signal responsive to the internal adjustment signal (V sen ).
1. A power measurement system for use on an integrated circuit for measuring the power used by the integrated circuit, said power measurement system comprising:
a low-dropout voltage regulator including a power transistor that couples a supply voltage to the integrated circuit as the supply voltage, said low-dropout voltage regulator providing an internal adjustment signal (V sen ) for adjusting the internal resistance of the power transistor; and
signal input means for receiving the internal adjustment signal (V sen ) and providing a power measurement signal responsive to the internal adjustment signal (V sen ).
2. The power measurement system as claimed in claim 1 , wherein said signal input means determines a current measurement (I dd ) based on the internal adjustment signal (V sen ) and estimates the power measurement signal based on the current measurement (I dd ).
3. The power measurement system as claimed in claim 1 , wherein said signal input means includes an analog-to-digital converter that samples and digitizes a voltage (V cl ) that is provided by a capacitor (C i ).
4. The power measurement system as claimed in claim 3 , wherein said signal input means further includes a first transistor and said internal adjustment signal (V sen ) is provided to a gate of the first transistor.
5. The power measurement system as claimed in claim 3 , wherein said signal input means further includes a current source for calibration.
6. The power measurement system as claimed in claim 5 , wherein said current source is coupled to the capacitor.
7. The power measurement system as claimed in claim 1 , wherein said signal input means includes a counter that measures a frequency of a voltage controlled oscillator.
8. The power measurement system as claimed in claim 7 , wherein said voltage controlled oscillator includes a plurality of inverters.
9. The power measurement system as claimed in claim 7 , wherein said internal adjustment signal (V sen ) is provided to a buffer amplifier, and the voltage controlled oscillator is coupled to an output of the buffer amplifier.
10. The power measurement system as claimed in claim 9 , wherein said internal adjustment signal (V sen ) is provided to a positive input of the buffer amplifier and the negative input of the buffer amplifier is coupled to an output of the buffer amplifier.
11. A power measurement system for use on an integrated circuit for measuring the power used by the integrated circuit, said power measurement system comprising:
a low-dropout voltage regulator including a power transistor that couples a supply voltage to the integrated circuit to be powered by the supply voltage, said low-dropout voltage regulator also including an error amplifier for providing an internal adjustment signal (V sen ) for adjusting the internal resistance of the power transistor; and
signal input means for receiving the internal adjustment signal (V sen ) determining a current measurement (I dd ) based on the internal adjustment signal (V sen ), and estimating a power measurement signal based on the current measurement (I dd ).
12. The power measurement system as claimed in claim 11 , wherein said signal input means includes an analog-to-digital converter that samples and digitizes a voltage (V cl ) that is provided by a capacitor (C i ).
13. The power measurement system as claimed in claim 12 , wherein said signal input means further includes a first transistor and said internal adjustment signal (V sen ) is provided to a gate of the first transistor.
14. The power measurement system as claimed in claim 12 , wherein said signal input means further includes a current source for calibration.
15. The power measurement system as claimed in claim 14 , wherein said current source is coupled to the capacitor.
16. The power measurement system as claimed in claim 11 , wherein said signal input means includes a counter that measures a frequency of a voltage controlled oscillator.
17. The power measurement system as claimed in claim 16 , wherein said voltage controlled oscillator includes a plurality of inverters.
18. The power measurement system as claimed in claim 16 , wherein said internal adjustment signal (V sen ) is provided to a buffer amplifier, and the voltage controlled oscillator is coupled to an output of the buffer amplifier.
19. A method of measuring power used by an integrated circuit, said method comprising the steps of:
receiving an internal adjustment signal (V sen ) from an error amplifier in a low-dropout voltage regulator that includes a power transistor for coupling a supply voltage to the integrated circuit to be powered by the supply voltage, said internal adjustment signal (V sen ) for adjusting the internal resistance of the power transistor; and
providing a power measurement signal responsive to the internal adjustment signal (V sen ).
20. The method as claimed in claim 19 , wherein said step of providing a power measurement signal responsive to the internal adjustment signal (V sen ) includes the steps of determining a current measurement (I dd ) based on the internal adjustment signal (V sen ) and estimating the power measurement signal based on the current measurement (I dd ).