IP Library Granted Patent US 8,501,578
Granted Patent B2
US 8,501,578 · App. 12/691,917 · Granted Aug 6, 2013

Semiconductor structure formed without requiring thermal oxidation

Inventor: Bishnu Prasanna Gogoi (Scottsdale, AZ)
Assignee: Estivation Properties LLC
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,501,578
App. No.
12/691,917
Granted
Aug 6, 2013
Kind
B2
Abstract

Briefly, in accordance with one or more embodiments, a semiconductor device is manufactured by forming at least two or more cavities below a surface of a semiconductor substrate wherein the at least two or more cavities are spaced apart from each other by a selected distance, filling at least a portion of the at least two or more cavities with a dielectric material to form at least two or more dielectric structures, removing a portion of the substrate between the at least two or more dielectric structures to form at least one additional cavity, and covering the at least one additional cavity.

Claims (28)

1. A method for manufacturing a semiconductor device, the method comprising:

forming at least two or more cavities below a surface of a semiconductor substrate wherein the at least two or more cavities are spaced apart from each other by a selected distance;

filling at least a portion of the at least two or more cavities with a dielectric material to form at least two or more dielectric structures;

removing a portion of the substrate between the at least two or more dielectric structures to form an additional cavity;

depositing a capping material on the at least two or more dielectric structures; and

covering the additional cavity and the capping material to form a sealed cavity.

2. The method of claim 1 , wherein said removing a portion of the substrate comprises creating an opening to the additional cavity, and wherein said depositing a capping material comprises decreasing a size of the opening to the additional cavity.

3. The method of claim 1 , wherein the capping material comprises an additional dielectric material.

4. The method of claim 3 , wherein the additional dielectric material comprises silicon oxide, silicon nitride, or combinations thereof.

5. The method of claim 4 , further comprising using a non-conformal deposition process to form the silicon oxide, silicon nitride, or combinations thereof.

6. The method of claim 1 , wherein the dielectric material comprises silicon oxide, silicon nitride, or combinations thereof.

7. The method of claim 6 , further comprising using a conformal deposition process to form the silicon oxide, silicon nitride, or combinations thereof.

8. The method of claim 1 , wherein the at least two or more cavities are formed using a wet chemical etch, a dry etch, a reactive ion etch, or combinations thereof.

9. The method of claim 1 , wherein the at least two or more cavities are formed using an anisotropic etch.

10. The method of claim 1 , wherein the additional cavity is formed using a wet chemical etch, a dry etch, a reactive ion etch, or combinations thereof.

11. The method of claim 1 , wherein the additional cavity is formed using an anisotropic etch.

12. The method of claim 1 , wherein said covering the additional cavity comprises forming an additional material over the additional cavity and the at least two or more dielectric structures.

13. The method of claim 12 , wherein the additional material comprises an additional dielectric material.

14. The method of claim 13 , wherein the additional dielectric material comprises silicon oxide, silicon nitride, or combinations thereof.

15. The method of claim 14 , wherein the silicon oxide, silicon nitride, or combinations thereof, is formed using a conformal or non-conformal deposition process.

16. The method of claim 15 , wherein the additional material comprises polysilicon, and wherein the polysilicon is at least partially oxidized such that the additional cavity is sealed by silicon oxide.

17. The method of claim 1 , wherein said filling at least a portion of the at least two or more cavities with a dielectric material comprises:

overfilling the at least two or more cavities with the dielectric material; and

removing a portion of the dielectric material above the surface of the substrate.

18. The method of claim 17 , wherein said removing comprises wet chemical etching, dry etching, reactive ion etching, chemical mechanical polishing (CMP), or combinations thereof.

19. The method of claim 1 , further comprising forming an additional dielectric material over the dielectric material.

20. The method of claim 19 , wherein the additional dielectric material comprises silicon oxide, silicon nitride, or combinations thereof.

21. The method of claim 20 , wherein the silicon oxide, silicon nitride, or combinations thereof is formed using a conformal or non-conformal deposition process.

Assignments (3)
MERGER Recorded Dec 30, 2015
From: ESTIVATION PROPERTIES LLC
To: XENOGENIC DEVELOPMENT LIMITED LIABILITY COMPANY
Reel/Frame 037384/0135 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2012
From: HVVI SEMICONDUCTOR, INC.
To: ESTIVATION PROPERTIES LLC
Reel/Frame 028644/0109 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2010
From: GOGOI, BISHNU PRASANNA
To: HVVI SEMICONDUCTORS, INC.
Reel/Frame 024157/0261 →
Continuity (1)
Related Publication 20110183490A1 · Jul 28, 2011