Semiconductor device with stacked semiconductor chips
View Patent ↗A semiconductor device includes first to third semiconductor chips. The second semiconductor chip is stacked over the first semiconductor chip. The third semiconductor chip is stacked over the second semiconductor chip. The second semiconductor chip shields the first semiconductor chip from noises generated by the third semiconductor chip. The second semiconductor chip shields the third semiconductor chip from noises generated by the first semiconductor chip.
1. A semiconductor device comprising:
a first semiconductor chip;
a second semiconductor chip stacked over the first semiconductor chip; and
a third semiconductor chip stacked over the second semiconductor chip,
wherein the second semiconductor chip shields the first semiconductor chip from noises generated by the third semiconductor chip, and the second semiconductor chip shields the third semiconductor chip from noises generated by the first semiconductor chip, and
wherein the second semiconductor chip is electrically connected to the third semiconductor chip.
2. The semiconductor device according to claim 1 , wherein outer edges of the first and third semiconductor chips are aligned to or inside an outer edge of the second semiconductor chip in plane view.
3. The semiconductor device according to claim 1 , wherein the first and third semiconductor chips are a radio frequency chip and a memory chip, respectively.
4. The semiconductor device according to claim 1 , wherein a surface of the second semiconductor chip is coated by a conductor.
5. The semiconductor device according to claim 1 , further comprising: a spacer between the first and second semiconductor chips.
6. The semiconductor device according to claim 1 , further comprising:
a wiring board having first and second regions, the first region being covered by the first semiconductor chip;
a plurality of first and second connection pads in the second region;
a plurality of first electrode pads aligned along sides of the first semiconductor chip, the plurality of first electrode pads being electrically connected to the plurality of first connection pads;
a plurality of second electrode pads aligned along sides of the second semiconductor chip, the plurality of second electrode pads being electrically connected to the plurality of second connection pads; and
a plurality of third and fourth electrode pads aligned along sides of the third semiconductor chip, the plurality of third electrode pads being electrically connected to the plurality of first connection pads, and the plurality of fourth electrode pads being electrically connected to the plurality of second electrode pads.
7. The semiconductor device according to claim 6 , further comprising:
a plurality of lands fixed to the wiring board, the plurality of lands being on an opposite side of the plurality of first and second connection pads with respect to the wiring board,
wherein the plurality of first connection pads are electrically connected to the plurality of lands.
8. The semiconductor device according to claim 6 , wherein
the plurality of first and third electrode pads are electrically connected to the plurality of first connection pads using a plurality of wires,
the plurality of second electrode pads are electrically connected to the plurality of second connection pads using a plurality of wires, and
the plurality of fourth electrode pads are electrically connected to the plurality of second electrode pads using a plurality of wires.
9. The semiconductor device according to claim 7 , wherein the plurality of first connection pads are electrically connected to the plurality of lands using a plurality of wires penetrating the wiring board.
10. The semiconductor device according to claim 6 , further comprising:
a seal covering the second region and the first to third semiconductor chips.
11. The semiconductor device according to claim 1 , further comprising:
a fourth semiconductor chip stacked over the third semiconductor chip,
wherein the second semiconductor chip shields the first semiconductor chip from noises generated by a set of the third and fourth semiconductor chips, and the second semiconductor chip shields the set of the third and fourth semiconductor chips from noises generated by the first semiconductor chip.
12. The semiconductor device according to claim 11 , wherein outer edges of the first, third, and fourth semiconductor chips are aligned to or inside an outer edge of the second semiconductor chip in plane view.
13. The semiconductor device according to claim 11 , further comprising:
a wiring board having first and second regions, the first region being covered by the first semiconductor chip;
a plurality of first and second connection pads in the second region;
a plurality of first electrode pads aligned along sides of the first semiconductor chip, the plurality of first electrode pads being electrically connected to the plurality of first connection pads;
a plurality of second electrode pads aligned along sides of the second semiconductor chip, the plurality of second electrode pads being electrically connected to the plurality of second connection pads;
a plurality of third electrode pads aligned along sides of the third semiconductor chip, the plurality of third electrode pads being electrically connected to the plurality of first connection pads; and
a plurality of fourth and fifth electrode pads aligned along sides of the fourth semiconductor chip, the plurality of fourth electrode pads being electrically connected to the plurality of first connection pads, and the plurality of fifth electrode pads being electrically connected to the plurality of second electrode pads.
14. The semiconductor device according to claim 13 , further comprising:
a plurality of lands fixed to the wiring board, the plurality of lands being on an opposite side of the plurality of first and second connection pads with respect to the wiring board,
wherein the plurality of first connection pads are electrically connected to the plurality of lands.
15. The semiconductor device according to claim 13 , wherein
the plurality of first, third, and fourth electrode pads are electrically connected to the plurality of first connection pads using a plurality of wires,
the plurality of second electrode pads are electrically connected to the plurality of second connection pads using a plurality of wires, and
the plurality of fifth electrode pads are electrically connected to the plurality of second electrode pads using a plurality of wires.
16. The semiconductor device according to claim 14 , wherein the plurality of first connection pads are electrically connected to the plurality of lands using a plurality of wires penetrating the wiring board.
17. The semiconductor device according to claim 13 , further comprising:
a seal covering the second region and the first to fourth semiconductor chips.
18. A semiconductor device comprising:
a first semiconductor chip including a main surface and a side surface defining an edge thereof;
a conductive layer staked over the first semiconductor chip and including a plane surface facing to the main surface without covering the side surface of the first semiconductor chip; and
a second semiconductor chip stacked over the conductive layer so that the conductive layer is disposed between the first and second semiconductor chips,
wherein the conductive layer is larger in size than each of the first and second semiconductor chips.
19. The semiconductor device according to claim 18 , further comprising:
a first bonding wire electrically coupling the conductive layer to the second semiconductor chip.
20. The semiconductor device according to claim 19 , further comprising:
a wiring board including a connection pad thereon, and provided over the first semiconductor chip, the first semiconductor chip being disposed between the wiring board and the conductive layer; and
a second bonding wire electrically coupling the connection pad of the wiring board to the conductive layer.
21. The semiconductor device according to claim 18 , wherein one of the first and second semiconductor chips is a radio frequency chip, the other of the first and second semiconductor chips is a memory chip.
22. The semiconductor device according to claim 18 , further comprising:
a third semiconductor chip stacked over the second semiconductor chip, the third semiconductor chip is smaller in size than the conductive layer.
23. The semiconductor device according to claim 18 , further comprising:
a spacer provided between the first semiconductor chip and the conductive layer, the spacer is smaller in size than the first semiconductor chip.
24. A semiconductor device comprising:
a wiring board;
a first semiconductor chip mounted over the wiring board;
a silicon substrate including first and second main surfaces opposite to each other and a conductive layer formed on the first main surface, the silicon substrate being stacked over the first semiconductor chip so that the second main surface of the silicon substrate faces the first semiconductor chip; and
a second semiconductor chip stacked over the conductive layer on the first main surface of the silicon substrate,
wherein the conductive layer is larger in size than each of the first and second semiconductor chips.
25. The semiconductor device according to claim 24 , further comprising:
a connection pad disposed on the wiring board;
a first bonding wire electrically coupling the connection pad of the wiring board to the conductive layer of the silicon substrate; and
a second bonding wire electrically coupling the conductive layer of the silicon substrate to the second semiconductor chip.
26. The semiconductor device according to claim 25 , wherein one of the first and second semiconductor chips is a radio frequency chip, the other of the first and second semiconductor chips is a memory chip.
27. The semiconductor device according to claim 25 , wherein the conductive layer is formed on an entire surface of the upper surface of the silicon substrate.
28. The semiconductor device according to claim 25 , further comprising;
a third semiconductor chip stacked over the second semiconductor chip, the third semiconductor chip is smaller in size than the conductive layer.
29. The semiconductor device according to claim 25 , further comprising:
a spacer provided between the first semiconductor chip and the silicon substrate, the spacer is smaller in size than the first semiconductor chip; and
a bonding wire electrically coupling the wiring board to the first semiconductor chip.