Failure analysis apparatus, method

1. A failure analysis apparatus comprising:

a host machine;

first and second microprocessors of an identical configuration, the first microprocessor being a known good device, while the second microprocessor being a target for failure analysis; and

first and second debug interface devices connecting the host machine to the first and second microprocessors, respectively,

the host machine controlling debugging of the first and second microprocessors, via the first and second debug interface devices, wherein the host machine comprises

a unit that causes the first and second microprocessors to execute identical debug operations in parallel, via the first and second debug interface devices, obtains internal information of the first and second microprocessors, via the first and second debug interface devices, and compares the internal information of the first and second microprocessors to perform failure analysis of the second microprocessor,

wherein the host machine sets a plurality of break points in respective programs of the first and second microprocessors via the first and second debug interface devices, and

in case the internal information obtained from the first and second microprocessors at a first break point matches and the internal information obtained from the first and second microprocessors at a second break point executed by the first and second microprocessors after the first break point does not match, as a subsequent operation, the host machine changes a debug command so that instructions between the first break point and the second break point are executed by step-execution, and supplies the changed debug command to the first and second microprocessors via the first and second debug interface devices.

2. The failure analysis apparatus according to claim 1 , wherein the host machine designates in advance a debug operation which is to be performed next in the first and second microprocessors when a mismatch in the internal information of the first and second microprocessors is detected.

3. A failure analysis apparatus comprising:

a host machine;

first and second microprocessors of an identical configuration, the first microprocessor being a known good device, while the second microprocessor being a target for failure analysis; and

first and second debug interface devices connecting the host machine to the first and second microprocessors, respectively,

the host machine controlling debugging of the first and second microprocessors, via the first and second debug interface devices, wherein the host machine comprises

a unit that causes the first and second microprocessors to execute identical debug operations in parallel, via the first and second debug interface devices, obtains internal information of the first and second microprocessors, via the first and second debug interface devices, and compares the internal information of the first and second microprocessors to perform failure analysis of the second microprocessor,

wherein the host machine sets a break point in a binary search manner in respective programs of the first and second microprocessors via the first and second debug interface devices,

wherein the host machine sets first and second break points corresponding to start and end of a search range in the respective programs of the first and second microprocessors via the first and second debug interface devices, and

in case the internal information obtained from the first and second microprocessors at the first break point matches, and the internal information obtained from the first and second microprocessors at the second break point executed by of the first and second microprocessors after the first break point does not match,

the host machine directs the first and second microprocessors via the first and second debug interface devices to set an intermediate point between the first break point and the second break point as a third break point.

4. The failure analysis apparatus according to claim 3 , wherein in case the first and second microprocessors each execute a program from program start as far as the third break point, and the internal information obtained from the first and second microprocessors at the third break point matches,

the host machine sets the third break point as a new first break point, and sets an intermediate point between the new first break point and the second break point as a third break point, and

in case internal information obtained from the first and second microprocessors at the third break point does not match,

the host machine directs the first and second microprocessors via the first and second debug interface devices to set the third break point as a new second break point, and an intermediate point between the new second break point and the first break point as a third break point.

5. A failure analysis apparatus comprising:

a host machine;

first and second microprocessors of an identical configuration, the first microprocessor being a known good device, while the second microprocessor being a target for failure analysis; and

first and second debug interface devices connecting the host machine to the first and second microprocessors, respectively,

the host machine controlling debugging of the first and second microprocessors, via the first and second debug interface devices, wherein the host machine comprises

a unit that causes the first and second microprocessors to execute identical debug operations in parallel, via the first and second debug interface devices, obtains internal information of the first and second microprocessors, via the first and second debug interface devices, and compares the internal information of the first and second microprocessors to perform failure analysis of the second microprocessor,

wherein in case internal information obtained from the first and second microprocessors at one break point does not match, the host machine, after writing at least a part of the internal information of the first microprocessor to the second microprocessor to set the second microprocessors to have the same information with regard to at least the part of the internal information thereof as that of the first microprocessor, performs control to carry out re-execution in the first and second microprocessor from an instruction subsequent to the one break point.

6. The failure analysis apparatus according to claim 5 , wherein the host machine performs re-execution as step-execution, and

in case the internal information obtained from the first and second microprocessors at one break point does not match,

the host machine stores mismatching information in a storage unit thereof; and

as a result of the step execution, if there are a plurality of items of the mismatching information stored in the storage unit,

the host machine extracts a common point of at least two items of mismatching information among the plurality of items of the mismatching information.