Manufacturing method of semiconductor memory device

1. A manufacturing method of a semiconductor device including sense amplifiers that amplifies a potential difference between bit lines, the method comprising:

forming a ring-shaped gate electrode and source and drain regions for transistors constituting the sense amplifiers;

forming an insulating layer over the transistors;

forming a mask layer on the insulating layer, the mask layer having a line-shaped opening that expose an area of the insulating layer covering respective portions of the source and drain regions of each of the transistors; and

forming a plurality of contact plugs each electrically connected to an associated one of the source and drain regions by using a line SAC (Self-Align Contact) technique in which the area of the insulation layer is selectively removed by use of the mask layer.

2. The method as claimed in claim 1 , wherein the opening is provided along a direction substantially orthogonal to the bit lines.

3. The method as claimed in claim 1 , wherein the transistors constituting a same sense amplifier are arranged along the bit lines.

4. A manufacturing method of a semiconductor device, comprising:

forming a plurality of substantially cylindrically-shaped gate electrodes covered with an insulation film;

forming drain regions and source regions on the semiconductor substrate to form a plurality of transistors, each of the drain regions and each of the source regions correspond to an associated one of the gate electrodes;

covering the transistors by an interlayer insulation layer;

forming a plurality of contact holes partitioned by the insulation films and the interlayer insulation layer from one another by selectively removing the interlayer insulation layer by using a mask formed on the interlayer insulation layer, the mask having a line-shaped opening positioned over respective parts of the source and drain regions of the transistors with an intervention of the interlayer insulation layer; and

forming a plurality of contact plugs that are embedded in the contact holes.

5. The method as claimed in claim 4 , further comprising defining an active region by forming a dielectric isolation region in the semiconductor substrate,

wherein the transistors are formed along the active region.

6. The method as claimed in claim 5 , wherein the opening is provided along the active region.

7. The method as claimed in claim 5 , wherein the transistors are formed so that a part of which is positioned on the dielectric isolation region.

8. The method as claimed in claim 5 , wherein

a plurality of dielectric isolation regions are provided, thereby defining a plurality of active regions in parallel to each other, and

the transistors are formed along a respective one of the active regions.

9. The method as claimed in claim 4 , wherein one of the drain region and the source region of each of the transistors is provided in an internal region surrounded by the cylindrically-shaped gate electrode, and the other one of the drain region and the source region of each of the transistors is provided in common to each of the transistors in an external region of the gate electrode.

10. The method as claimed in claim 9 , wherein the drain region is provided for each of the transistors in the internal region, and the source region is provided in common to each of transistors in the external region.

11. A manufacturing method of a semiconductor device, comprising:

defining an active region by a dielectric isolation region;

forming a plurality of ring-gate structures for a plurality of transistors along the active region, each of the ring-gate structures having an upper surface and a side surface covered with an insulation film;

forming a plurality of first regions each of which serves as one of a source region and a drain region of an associated one of the transistors, the first regions being portioned on the active region corresponding to an internal portion surrounded by an associated one of the ring-gate structures;

forming a plurality of second regions each of which serves as other one of the source region and the drain region in common to each of the transistors, the second regions being portioned on the active region corresponding to an external portion of each of the ring-gate structures;

covering the active region and the ring-gate structures by an interlayer insulation layer;

forming a mask layer on the interlayer insulation layer having a line-shaped opening positioned over the internal portions of the ring-gate structures, a part of the ring-gate structures, and portions sandwiched by adjacent ring-gate structures with an intervention of the interlayer insulation layer;

selectively removing the interlayer insulation layer by using the mask layer and the insulation film as a mask to form contact holes; and

forming contact plugs within the contact holes, each of the contact plugs being connected to an associated one of the source and drain regions.

12. The method as claimed in claim 11 , wherein the opening is provided in parallel to a row of the ring-gate structures.

13. The method as claimed in claim 11 , wherein

the active region is included in a plurality of mutually parallel active regions, and

the row of the ring-gate structures is formed on an associated one of the active regions.

14. The method of as claimed in claim 11 , wherein each of the first regions is the drain region of each of the transistors, and each of the second regions is the source region of each of the transistors.