Nonvolatile semiconductor memory device and method for manufacturing the same
View Patent ↗A split gate type nonvolatile semiconductor memory device having a FinFET structure includes a semiconductor substrate, parallel trenches on a surface of the semiconductor substrate, and select and memory gate electrodes perpendicular to the trenches. While either the select or the memory gate electrodes are formed prior to the other gate electrodes, each remaining gate electrode is formed adjacent to a side wall of each of the gate electrodes. The semiconductor memory device includes source/drain regions each formed between each pair of the select gate electrodes and between each pair of the memory gate electrodes in protruding portions between each pair of the trenches. A difference between heights of the select gate electrodes and the memory gate electrodes is equal to or greater than a difference between heights of insulation layers formed on the bottom of each of the trenches and the source/drain regions.
1. A nonvolatile semiconductor memory device comprising:
a semiconductor substrate having a plurality of trenches in parallel with each other on a surface of the semiconductor substrate;
insulation layers each formed on a bottom surface of each of the plurality of trenches;
a select gate electrode formed in a direction perpendicular to the plurality of trenches on the surface of the semiconductor substrate and side walls of the plurality of trenches via a first gate insulating film;
a memory gate electrode formed on the surface of the semiconductor substrate and side walls of the plurality of trenches via a second gate insulating film formed of a multilayer film including a charge storage layer, the memory gate electrode formed adjacent to the select gate electrode via an insulating film in a direction perpendicular to the plurality of trenches; and
source/drain regions each formed on the surface of the semiconductor substrate between each pair of the plurality of trenches and sandwiching the select gate electrode and the memory gate electrode;
wherein a difference between a height of a surface of the select gate electrode and a height of a surface of the memory gate electrode is equal to or greater than a difference between a height of a surface of the insulation layers each formed on the bottom surface of each of the trenches and a height of a surface of the source drain regions.
2. The nonvolatile semiconductor memory device according to claim 1 , wherein the height of the surface of the select gate electrode is greater than the height of the surface of the memory gate electrode, and the memory gate electrode is formed adjacent to a side wall of the select gate electrode.
3. The nonvolatile semiconductor memory device according to claim 2 , wherein the memory gate electrode comprises first and second memory gate electrodes sandwiching the select gate electrode via the insulating film, and wherein each pair of the source/drain regions sandwiches the first memory gate electrode, the select gate electrode, and the second memory gate electrode and are formed adjacent to a side of the first memory gate electrode or the second memory gate electrode, the side being opposite to the select gate electrode.
4. The nonvolatile semiconductor memory device according to claim 2 ,
wherein, assuming that the memory gate electrode is a first memory gate electrode, a second memory gate electrode is formed adjacent to the first memory gate electrode via the select gate electrode,
wherein the second memory gate electrode is formed on the surface of the semiconductor substrate and side walls of the plurality of trenches via the second gate insulating film and formed adjacent to the select gate electrode via an insulating film in a direction perpendicular to the plurality of trenches, and
wherein each pair of the source drain regions sandwiches the first memory gate electrode, the select gate electrode, and the second memory gate electrode arranged in this order.
5. The nonvolatile semiconductor memory device according to claim 1 , wherein the height of the surface of the memory gate electrode is greater than the height of the surface of the select gate electrode, and the select gate electrode is formed adjacent to a side wall of the memory gate electrode.
6. The nonvolatile semiconductor memory device according to claim 2 , wherein dummy layers are formed on top of the select gate electrode, and the height of the surface of the select gate electrode includes heights of the dummy layers, and wherein the memory gate electrode is formed adjacent to a side wall of the select gate electrode of which height includes the heights of the dummy layers.
7. The nonvolatile semiconductor memory device according to claim 6 , wherein the dummy layers comprise a silicon nitride film.
8. The nonvolatile semiconductor memory device according to claim 5 , wherein dummy layers are formed on top of the memory gate electrode, the height of the surface of the memory gate electrode includes heights of the dummy layers, and the select gate electrode is formed adjacent to a side wall of the memory gate electrode of which height includes heights of the dummy layers.
9. The nonvolatile semiconductor memory device according to claim 1 , wherein metal wirings are formed above the memory gate electrode and the select gate electrode via an interlayer insulating film that covers the surface of the semiconductor substrate, and wherein the source drain regions are connected to the metal wirings via contacts formed in the interlayer insulating film.