IP Library Granted Patent US 8,278,657
Granted Patent B2
US 8,278,657 · App. 12/699,974 · Granted Oct 2, 2012

Transistor, semiconductor device including the transistor, and manufacturing method of the transistor and the semiconductor device

Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 8,278,657
App. No.
12/699,974
Granted
Oct 2, 2012
Kind
B2
Abstract

To suppress deterioration in electrical characteristics in a transistor including an oxide semiconductor layer or a semiconductor device including the transistor. In a transistor in which a channel layer is formed using an oxide semiconductor, a silicon layer is provided in contact with a surface of the oxide semiconductor layer. Further, the silicon layer is provided in contact with at least a region of the oxide semiconductor layer, in which a channel is formed, and a source electrode layer and a drain electrode layer are provided in contact with regions of the oxide semiconductor layer, over which the silicon layer is not provided.

Claims (25)

1. A transistor comprising:

a gate electrode;

a gate insulating layer provided over the gate electrode;

an oxide semiconductor layer provided over the gate insulating layer and overlapping with the gate electrode;

a silicon layer provided over and in contact with a surface of the oxide semiconductor layer; and

a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer.

2. The transistor according to claim 1 ,

wherein the silicon layer is provided over and in contact with a part of the surface of the oxide semiconductor layer, and

wherein the source electrode layer and the drain electrode layer are provided over and in contact with at least a part of the surface of the oxide semiconductor layer, over which the silicon layer is not provided.

3. The transistor according to claim 2 ,

wherein a first low-resistance region serving as a source region is provided in a region of the oxide semiconductor layer, which is in contact with the source electrode layer, and

wherein a second low-resistance region serving as a drain region is provided in a region of the oxide semiconductor layer, which is in contact with the drain electrode layer.

4. The transistor according to claim 1 , wherein the oxide semiconductor layer includes at least one of indium, zinc, and gallium.

5. A semiconductor device comprising the transistor according to claim 1 .

6. A manufacturing method of a transistor, comprising the steps of:

forming a gate electrode over a substrate;

forming a gate insulating layer over the gate electrode;

forming an oxide semiconductor layer over the gate insulating layer so as to overlap with the gate electrode;

forming a silicon layer so as to cover the oxide semiconductor layer;

etching the silicon layer to expose a part of the oxide semiconductor layer;

forming a conductive film over the silicon layer and the oxide semiconductor layer; and

etching the conductive film to form a source electrode layer and a drain electrode layer.

7. The manufacturing method of a transistor according to claim 6 ,

wherein the source electrode layer and the drain electrode layer are formed in contact with at least parts of the exposed oxide semiconductor layer.

8. The manufacturing method of a transistor according to claim 6 , wherein the silicon layer is formed by a DC sputtering method.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2010
From: SAKATA, JUNICHIRO; GODO, HIROMICHI; SHIMAZU, TAKASHI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 023896/0741 →
Priority Claims (1)
JP 2009-030969 · Feb 13, 2009 · national
Continuity (1)
Related Publication 20100207118A1 · Aug 19, 2010