Clock signal noise shaping

1. A clock circuit, comprising:

a filter coupled to receive a first input clock signal, wherein the first input clock signal is noncompliant with a phase parameter of a serial link specification for a serial link owing to phase noise;

the filter coupled to provide an output clock signal, wherein the phase noise of the first input clock signal is shaped by the filter to reform the first input signal in order to provide the output clock signal for compliance with the phase parameter of the serial link specification for the serial link for at least a gigabit per second speed;

the filter for filtering noise of the first input clock signal to shape the phase noise to provide the output clock signal; and

a lock loop circuit directly connected to the filter to receive the output clock signal.

2. The clock circuit according to claim 1 , wherein the lock loop circuit is a phase lock loop.

3. The clock circuit according to claim 1 , wherein the lock loop circuit is a delay lock loop.

4. The clock circuit according to claim 1 , wherein the filter is a low-pass filter.

5. The clock circuit according to claim 1 , wherein the filter is a band-pass filter.

6. The clock circuit according to claim 1 , wherein the filter is a high-pass filter.

7. The clock circuit according to claim 1 , wherein the filter is an equalization filter.

8. The clock circuit according to claim 1 , wherein the filter is a programmable filter.

9. The clock circuit according to claim 8 , wherein the programmable filter has programmable poles and zeroes for noise shaping.

10. The clock circuit according to claim 1 , wherein the filter is further coupled to receive a second input clock signal.

11. The clock circuit according to claim 10 , further comprising a buffer coupled to the filter to provide the first input clock signal and the second input clock signal to the filter, the first input clock signal and the second input clock signal being at least approximately 180 degrees out-of-phase with respect to one another.

12. The clock circuit according to claim 11 , wherein the buffer is coupled to receive a first serial reference clock signal and a second serial reference clock signal to respectively provide the first input clock signal and the second input clock signal, the first serial reference clock signal and the second serial reference clock signal being at least approximately 180 degrees out-of-phase with respect to one another.

13. The clock circuit according to claim 12 , further comprising a phase lock loop coupled to receive the output clock signal as a single signal and configured to provide a first output clock signal and a second output clock signal, the first output clock signal and the second output clock signal being at least approximately 180 degrees out-of-phase with respect to one another.

14. The clock circuit according to claim 13 , wherein:

the first output clock signal and the second output clock signal each at least meet the phase parameter of the serial link specification for the serial link;

the phase lock loop includes a programmable counter for frequency translation; and

the filter, the buffer, and the phase lock loop are all formed on a same integrated circuit chip.

15. A method for adjustment of phase noise, comprising:

obtaining input clock signaling having the phase noise;

filtering the input clock signal to adjust the phase noise to provide output clock signaling;

wherein the filtering includes:

programming the filter to shape the phase noise to reform the input clock signaling; and

shaping the phase noise responsive to the programming to at least meet a specification for the phase noise for a serial link for at least a gigabit per second speed;

providing the output clock signal directly to a phase lock loop;

programming a counter of the phase lock loop;

translating a first frequency of the input clock signaling to a second frequency different from the first frequency; and

outputting operative clock signaling at the second frequency.