Semiconductor storage device and control method of the same
View Patent ↗A semiconductor storage device includes a timing allocation unit that sets refresh timing to preferentially perform a refresh operation for maintaining data and data access timing to preferentially perform a data access operation for reading or writing the data in accordance with a clock signal with respect to each memory bank including a plurality of memory cells, and a waiting unit that waits start of the data access operation until the data access timing is started in a case where a request for the data access operation is made during the refresh timing and waits start of the refresh operation until the refresh timing is started in a case where a request for the refresh operation is made during the data access timing.
1. A semiconductor storage device comprising:
a timing allocation unit that sets refresh timing to perform a refresh operation for maintaining data and data access timing to perform a data access operation for reading or writing the data in accordance with a clock signal with respect to each memory bank including a plurality of memory cells; and
a waiting unit that waits start of the data access operation until the data access timing is started in a case where a request for the data access operation is made during the refresh timing, and waits start of the refresh operation until the refresh timing is started in a case where a request for the refresh operation is made during the data access timing,
wherein the semiconductor storage device is configured so that a clock edge at which the request for the refresh operation is made according to
tRC=n*tCK
where tRC is a memory access time, tCK is a clock cycle and n is a positive number selected in accordance with memory capacity.
2. The semiconductor storage device according to claim 1 , wherein the refresh timing and the data access timing are respectively set in such a way that periods equivalent to a plurality of edges of the clock signal are repeated alternately.
3. A control method of a semiconductor storage device comprising:
setting refresh timing to perform a refresh operation for maintaining data and data access timing to perform a data access operation for reading or writing the data in accordance with a clock signal with respect to each memory bank including a plurality of memory cells;
waiting start of the data access operation until the data access timing is started in a case where a request for the data access operation is made during the refresh timing; and
waiting start of the refresh operation until the refresh timing is started in a case where a request for the refresh operation is made during the data access timing,
wherein a clock edge at which the request for the refresh operation is made according to
tRC=n*tCK
where tRC is a memory access time, tCK is a clock cycle and n is a positive number selected in accordance with memory capacity.
4. The control method of a semiconductor storage device according to claim 3 , wherein the refresh timing and the data access timing are respectively set in such a way that time periods equivalent to a plurality of edges are repeated alternately.
5. The semiconductor storage device according to claim 1 , wherein n=8.
6. The control method of a semiconductor storage device according to claim 3 , wherein n=8.
7. The semiconductor storage device according to claim 1 , wherein the refresh request to each memory bank is requested at m*tRC, where m is set by a timer.
8. The control method of a semiconductor storage device according to claim 3 , wherein the refresh request to each memory bank is requested at m*tRC, where m is set by a timer.
9. The semiconductor storage device according to claim 7 , wherein a timing control signal READY at m*(n+n′) makes the actual refresh request when there is a timer request to the clock signal.
10. The control method of a semiconductor storage device according to claim 8 , wherein a timing control signal READY at m*(n+n′) makes the actual refresh request when there is a timer request to the clock signal.
11. The semiconductor storage device according to claim 1 , wherein the refresh request to each memory bank is requested at m*tRC, where m is set by an external command.
12. The control method of a semiconductor storage device according to claim 3 , wherein the refresh request to each memory bank is requested at m*tRC, where m is set by an external command.
13. The semiconductor storage device according to claim 1 , wherein the refresh request to each memory bank is requested at m*tRC, where m is set by a timer, and
m*(n+n′) where n′<n determines when a timing control signal READY is issued.
14. The control method of a semiconductor storage device according to claim 3 , wherein the refresh request to each memory bank is requested at m*tRC, where m is set by a timer, and
m*(n+n′) where n′<n determines when a timing control signal READY is issued.