IP Library Granted Patent US 8,319,246
Granted Patent B2
US 8,319,246 · App. 12/706,366 · Granted Nov 27, 2012

Semiconductor device and method for manufacturing same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,319,246
App. No.
12/706,366
Granted
Nov 27, 2012
Kind
B2
Abstract

A semiconductor device includes: a semiconductor structure unit; an interconnect layer provided on the major surface side of the semiconductor structure unit; an electrode pad provided on a surface of the interconnect layer on a side opposite to a surface on which the semiconductor structure unit is provided, and the electrode pad electrically connected to the interconnect layer; a plurality of metal pillars joined to the electrode pad separately from each other; and an external terminal provided commonly at tips of the plurality of metal pillars, the metal pillars having an area in a plan view smaller than an area in a plan view of the external terminal.

Claims (44)

1. A semiconductor device comprising:

a semiconductor structure unit including a major surface;

an interconnect layer provided on the major surface side of the semiconductor structure unit;

an electrode pad provided on a surface of the interconnect layer on a side opposite to a surface on which the semiconductor structure unit is provided, and the electrode pad electrically connected to the interconnect layer;

a plurality of metal pillars joined to the electrode pad separately from each other; and

an external terminal provided commonly at tips of the plurality of metal pillars,

the metal pillars having an area in a plan view smaller than an area in a plan view of the external terminal,

wherein the semiconductor structure unit includes a light-emitting layer.

2. The device according to claim 1 , wherein a pad commonly connected to the plurality of metal pillars is provided at the tips of the metal pillars, and the external terminal is joined to the pad.

3. The device according to claim 1 , wherein the tips of the plurality of metal pillars are entered into the external terminal, and the external terminal covers a periphery of the tips of the plurality of metal pillars.

4. The device according to claim 3 , wherein the metal pillars are made of a material having a higher coefficient of thermal conductivity than the external terminal.

5. The device according to claim 1 , wherein a periphery of the metal pillars is covered with a resin.

6. The device according to claim 1 , wherein the plurality of metal pillars are laid out equally in a planar direction of the corresponding electrode pad.

7. A method for manufacturing a semiconductor device comprising:

forming an interconnect layer on a major surface of a semiconductor structure unit;

forming an electrode pad on a surface of the interconnect layer on a side opposite to a surface on which the semiconductor structure unit is provided;

forming an insulating member covering the electrode pad;

forming a plurality of holes penetrating through the insulating member to reach the electrode pad in the insulating member;

forming metal pillars in the holes; and

providing an external terminal commonly joined to tips of the plurality of metal pillars and the external terminal having an area in a plan view larger than an area in a plan view of each of the metal pillars.

8. The method according to claim 7 , wherein

the forming the metal pillars includes forming the metal pillars so that the tips of the metal pillars are protruded from the insulating member, and

the providing the external terminal includes providing the external terminal so that the external terminal covers the protruding metal pillars.

9. The method according to claim 7 , wherein

the forming the metal pillars includes forming a metal film on an exposed surface of the insulating member including inside of the holes by plating.

10. The method according to claim 9 , wherein, after forming the metal film, selective pattern plating is performed to form the external terminal at a portion opposed to the metal pillars.

11. The method according to claim 9 , wherein a portion of the metal film opposed to the electrode pad via the metal pillars is formed in a plate shape.

12. The method according to claim 7 , wherein pattern plating is performed in a state where a plating resist is selectively formed on a surface of the insulating member to form the metal pillars in the holes.

13. The method according to claim 12 , wherein

the forming the plating resist includes:

forming a resist film over a substantially entire surface of the insulating member; and

forming an opening communicating with the holes at a portion of the resist film opposed to the holes, and

the metal pillars are formed also in the opening of the resist film.

14. The method according to claim 13 , wherein, after forming the metal pillars, plating solution is changed to perform plating while leaving the plating resist to form the external terminal at the tips of the metal pillars.

15. The method according to claim 13 , wherein

the forming the metal pillars includes:

forming the metal pillars in the holes and in the opening so that the tips of the metal pillars exist within the opening; and

removing the plating resist to protrude the tips of the metal pillars from the insulating member.

16. The method according to claim 14 , wherein, after forming the external terminal, the plating resist is removed and the external terminal is melted to adhere the external terminal also to a periphery of the tips of the plurality of metal pillars.

17. The method according to claim 7 , including forming a semiconductor layer including a light-emitting layer on a substrate as the semiconductor structure unit.

18. The method according to claim 17 , including:

forming a dividing trench penetrating through the insulating member, the interconnect layer, and the semiconductor layer to reach the substrate; and

removing the substrate after forming the external terminal.

19. The method according to claim 18 , wherein an interface between the substrate and the semiconductor layer is irradiated with laser light to separate the substrate and the semiconductor layer.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 63256 FRAME: 350. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 3, 2024
From: SMART HANDOVER LLC
To: SEMILED INNOVATIONS LLC
Reel/Frame 069112/0605 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2023
From: SEOUL SEMICONDUCTOR CO., LTD.
To: SMART HANDOVER LLC
Reel/Frame 063256/0265 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2023
From: SMART HANDOVER LLC
To: SEMILED INNOVATIONS LLC
Reel/Frame 063256/0350 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2020
From: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
To: SEOUL SEMICONDUCTOR CO., LTD.
Reel/Frame 052316/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2020
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA ELECTRONIC DEVICES AND STORAGE CORPORATION
Reel/Frame 051691/0442 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2010
From: SUGIZAKI, YOSHIAKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 023948/0775 →