Apparatus and method for extended nitride layer in a flash memory
A method and apparatus for storing information is provided. A core region of memory includes a semiconductor layer, at least one shallow trench, an insulator, and a charge-trapping layer. The semiconductor layer includes at least one source/drain region, and the insulator disposed above the source/drain region. The charge trapping layer is within the insulator, and the charge trapping layer is above the entire width of the source/drain region, and extends at least one angstrom beyond the width of the source/drain region, so that a portion the charge trapping layer extends into at least one shallow trench.
1. A device for storing information, comprising:
a core region of memory, including:
a semiconductor layer, including a first source/drain region;
a first shallow trench;
an insulator disposed above the first source/drain region; and
a charge trapping layer disposed within the insulator, wherein the charge trapping layer is above the entire width of the first source/drain region, and extends at least one angstrom beyond the width of the first source/drain region, such a portion the charge trapping layer extends into the first shallow trench.
2. The device of claim 1 , wherein
the insulator extends at least thirty angstroms beyond the width of the source/drain region.
3. The device of claim 1 , wherein
the charge trapping layer is curved upwards such that an upper part of the charge trapping layer extends at least thirty angstroms above a lower part of the charge trapping layer.
4. The device of claim 1 , wherein
a top of the source/drain region is curved.
5. The device of claim 1 , wherein
the core region of memory employs self-aligned shallow trench isolation.
6. The device of claim 1 , wherein
the charge trapping layer includes means for charge trapping, or wherein the insulator includes means for electrical isolation.
7. A machine-readable storage medium that includes an electronic design file that is arranged to control a fabrication of the device of claim 1 .
8. A method, comprising transmitting, over a network, an article of manufacture including a machine-readable medium that includes an electronic design file that is arranged to control a fabrication of the device of claim 1 .
9. The device of claim 1 , wherein
the charge trapping layer is a nitride.
10. The device of claim 9 , wherein
the nitride is silicon rich nitride.
11. The device of claim 1 , wherein
the insulator is an oxide.
12. The device of claim 11 , wherein
the oxide is silicon dioxide.
13. The device of claim 1 , wherein
the core region of memory further includes a polysilicon layer that is disposed above the insulator.
14. The device of claim 13 , wherein
the charge storage layer is wrapped around at least a portion of the polysilicon layer.
15. The device of claim 13 , wherein
the polysilicon layer has bottom corners near the charge trapping layer, wherein the bottom corners of the polysilicon line are rounded.
16. A device for storing information, comprising:
a core region of memory, including:
a semiconductor layer, including a first source/drain region;
a first shallow trench that is adjacent to the first source/drain region;
a second shallow trench that is adjacent to the first source/drain region;
an oxide-nitride-oxide (ONO) layer disposed above the first source/drain region, wherein the ONO layer includes a nitride layer that is above the entire width of the first source/drain region, and extends at least one angstrom beyond the width of the first source/drain region, such that a portion of the nitride layer extends into the first shallow trench.
17. The device of claim 16 , wherein
the core region of memory employs self-aligned shallow trench isolation.
18. A method for storing information, comprising:
causing a memory device to perform a data access, wherein the memory device includes:
a core region of memory, including:
a semiconductor layer, including a first source/drain region;
a first shallow trench;
an insulator disposed above the first source/drain region; and
a charge trapping layer disposed within the insulator, wherein the charge trapping layer is above the entire width of the first source/drain region, and extends at least one angstrom beyond the width of the first source/drain region, such a portion the charge trapping layer extends into first shallow trench.