Semiconductor device and manufacturing method thereof
View Patent ↗A semiconductor device includes: a lower layer interconnection formed on a chip; an upper layer interconnection formed in an upper layer above the lower layer interconnection above the chip; an interconnection via formed to electrically connect the lower layer interconnection and the upper layer interconnection; a via-type electric fuse formed to electrically connect the lower layer interconnection and the upper layer interconnection. The fuse is cut through heat generation, and a sectional area of the fuse is smaller than a sectional area of the upper layer interconnection and a via diameter of the fuse is smaller than that of the interconnection via.
1. A semiconductor device comprising:
a lower layer interconnection formed on a chip;
an upper layer interconnection formed in an upper layer above said lower layer interconnection above said chip;
an interconnection via formed to electrically connect said lower layer interconnection and said upper layer interconnection;
a via-type electric fuse formed to electrically connect said lower layer interconnection and said upper layer interconnection, wherein said fuse is cut through heat generation,
wherein a sectional area of said fuse is smaller than a sectional area of said upper layer interconnection and a via diameter of said fuse is smaller than that of said interconnection via.
2. The semiconductor device according to claim 1 , wherein the sectional area of said upper layer interconnection is equal to or more than 1.8 times the sectional area of said fuse.
3. The semiconductor device according to claim 1 , further comprising:
a non-volatile memory which comprises said fuse and said interconnection via.
4. The semiconductor device according to claim 2 , wherein the via diameter of said interconnection via is equal to or more than 1.8 times the via diameter of said fuse.