Semiconductor device having output driver

1. A semiconductor device comprising:

a DLL circuit that receives a first clock signal and generates a second clock signal whose phase is controlled with respect to the first clock signal;

an output driver that outputs data in synchronization with the second clock signal; and

a mode register that indicates a swing capability of the output driver, wherein

the DLL circuit includes:

a delay line that delays the first clock signal to generate the second clock signal;

a replica driver that is a replica of the output driver and receives the second clock signal to generate a third clock signal;

a phase determination circuit that compares a phase of the first clock signal to a phase of the third clock signal; and

a control circuit that adjusts a delay amount of the delay line based on a determination result of the phase determination circuit, and wherein

a swing capability of the replica driver is variable based on a swing capability of the output driver indicated in the mode register.

2. The semiconductor device as claimed in claim 1 , wherein

a swing capability of the replica driver is set to be relatively large when a swing capability of the output driver indicated in the mode register is set to be relatively large, and

a swing capability of the replica driver is set to be relatively small when a swing capability of the output driver indicated in the mode register is set to be relatively small.

3. The semiconductor device as claimed in claim 1 , wherein

the output driver is configured to have a plurality of unit output drivers connected to each other in parallel,

the replica driver is configured to have a plurality of unit replica drivers connected to each other in parallel,

a swing capability of the output driver is variable by changing number of unit output drivers to be activated among the unit output drivers, and

a swing capability of the replica driver is variable by changing number of unit replica drivers to be activated among the unit replica drivers.

4. A semiconductor device comprising:

a DLL circuit that generates an internal clock signal whose phase is controlled;

an output driver that outputs data in synchronization with the internal clock signal; and

a mode register that indicates a swing capability of the output driver, wherein

the DLL circuit makes a phase of the internal clock signal relatively earlier when a swing capability of the output driver indicated in the mode register is set to be relatively large and,

the DLL circuit relatively delays the phase of the internal clock signal when a swing capability of the output driver indicated in the mode register is set to be relatively small.

5. The semiconductor device as claimed in claim 4 , wherein

the DLL circuit includes a delay line that delays an external clock signal to generate the internal clock signal,

the DLL circuit sets a delay amount of the delay line to be relatively small when a swing capability of the output driver indicated in the mode register is set to be relatively large, and

the DLL circuit sets the delay amount of the delay line to be relatively large when a swing capability of the output driver indicated in the mode register is set to be relatively small.

6. The semiconductor device as claimed in claim 4 , wherein

the output driver is configured to have a plurality of unit output drivers connected to each other in parallel, and

a swing capability of the output driver is variable by changing number of unit output drivers to be activated among the unit output drivers.

7. A semiconductor device comprising:

an output driver configured to output an output signal in response to a first clock signal; and

a DLL circuit configured to receive a second clock signal and delay the second clock signal by a delay amount to produce the first clock signal, the DLL circuit including a replica driver which is a replica of the output driver, the replica driver receiving the first clock signal to control the delay amount,

wherein a swing capability of the output driver is variable based on a first signal; and

wherein a swing capability of the replica driver is variable based on a second signal.

8. The semiconductor device as claimed in claim 7 , wherein the first and second signals are the same signal.

9. The semiconductor device as claimed in claim 7 , further comprising a mode register which outputs the first and second signals.

10. The semiconductor device as claimed in claim 9 , wherein the first and second signals are the same signal.

11. The semiconductor device as claimed in claim 9 , further comprising:

a command decoder which inputs a command signal; and

an address circuit which inputs an address signal,

wherein the mode register outputs the first and second signals based on outputs from the command decoder and the address circuit.

12. The semiconductor device as claimed in claim 7 ,

wherein the output driver includes a plurality of output driving circuits, and each of the output driving circuit outputs the output signal when activated; and

wherein the output driving circuits receive different control signals so that each of the output driving circuits is individually activated.

13. The semiconductor device as claimed in claim 12 ,

wherein the replica driver includes a plurality of replica driving circuits, and each of the replica driving circuit receives the first clock signal;

wherein each of the replica driving circuits outputs a replica clock signal when activated to control the delay amount; and

wherein the replica driving circuits receive the different control signals so that each of the replica driving circuits is individually activated.