IP Library Granted Patent US 8,350,285
Granted Patent B2
US 8,350,285 · App. 12/710,829 · Granted Jan 8, 2013

Semiconductor light-emitting device and method for manufacturing same

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,350,285
App. No.
12/710,829
Granted
Jan 8, 2013
Kind
B2
Abstract

A semiconductor light-emitting device of the invention includes: a semiconductor layer including a light-emitting layer and having a first major surface and a second major surface opposite to the first major surface; a phosphor layer facing to the first major surface; an interconnect layer provided on the second major surface side and including a conductor and an insulator; and a light-blocking member provided on a side surface of the semiconductor layer and being opaque to light emitted from the light-emitting layer.

Claims (30)

1. A semiconductor light-emitting device comprising:

a first semiconductor layer having a first major surface and a second major surface opposite to the first major surface;

a second semiconductor layer provided on the second major surface of the first semiconductor layer and including a light-emitting layer;

an n-side electrode provided on the second major surface of the first semiconductor layer;

a p-side electrode provided on a surface of the second semiconductor layer, the surface being an opposite side to the first semiconductor layer;

an insulating film provided on the p-side electrode and the n-side electrode, the insulating film having a first opening which reaches the p-side electrode and a second opening which reaches the n-side electrode;

a p-side interconnect provided on the insulating film and provided in the first opening, the p-side interconnect being connected to the p-side electrode;

an n-side interconnect provided on the insulating film and provided in the second opening, the n-side interconnect being connected to the n-side electrode;

a p-side metal pillar provided on the p-side interconnect, the p-side metal pillar having a first exposed end surface;

an n-side metal pillar provided on the n-side interconnect, the n-side metal pillar having a second exposed end surface;

a phosphor layer facing to the first major surface; and

a light-blocking member provided on a side surface of the first semiconductor layer and being opaque to light emitted from the light-emitting layer.

2. The device of claim 1 , wherein the light-blocking member is provided so as to surround the first semiconductor layer in a plan view.

3. The device of claim 2 , wherein

a planar size of the second semiconductor layer being smaller than a planar size of the first semiconductor layer,

the n-side interconnect is electrically connected the first semiconductor layer and the light-blocking member, and the p-side interconnect is electrically connected the second semiconductor layer.

4. The device of claim 1 , wherein

a planar size of the second semiconductor layer being smaller than a planar size of the first semiconductor layer,

the n-side interconnect is electrically connected the first semiconductor layer and the light-blocking member, and the p-side interconnect is electrically connected the second semiconductor layer.

5. The device of claim 1 , wherein

a planar size of the second semiconductor layer being smaller than a planar size of the first semiconductor layer,

the n-side interconnect is electrically connected the first semiconductor layer, and the p-side interconnect is electrically connected the second semiconductor layer and separated from the light-blocking member.

6. The device of claim 1 , wherein the light-blocking member includes:

a metal covering a side surface of the second semiconductor layer via an insulator; and

a resin surrounding the side surface outside the metal.

7. The device of claim 1 , further comprising

a sealing resin covering around the p-side metal pillar and the n-side metal pillar.

8. The device of claim 7 , wherein a part of the sealing resin covers the side surface of the first semiconductor layer as the light-blocking member.

9. The device of claim 1 , wherein a trench dividing the first semiconductor layer is formed in an end portion of the first semiconductor layer, and a metal is provided in the trench as the light-blocking member.

10. The device of claim 9 , wherein an end surface of the first semiconductor layer outside the trench is covered with a resin opaque to the light emitted by the light-emitting layer.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2018
From: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 046986/0159 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2018
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 046364/0164 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2010
From: SUGIZAKI, YOSHIAKI; KOJIMA, AKIHIRO; OBATA, SUSUMU
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 023978/0236 →
Priority Claims (1)
JP 2009-220434 · Sep 25, 2009 · national
Continuity (1)
Related Publication 20110073889A1 · Mar 31, 2011