THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE HAVING THE SAME
A thin film transistor, a method of fabricating the same, and an organic light emitting diode display device having the same, the thin film transistor including: a substrate; a silicon layer formed on the substrate; a diffusion layer formed on the silicon layer; a semiconductor layer that is crystallized using a metal catalyst, formed on the diffusion layer; a gate electrode disposed on the diffusion layer, facing a channel region of the semiconductor layer; a gate insulating layer disposed between the gate electrode and the semiconductor layer; and source and drain electrodes electrically connected to source and drain regions of the semiconductor layer.
1 . A thin film transistor comprising:
a substrate;
a silicon layer disposed on the substrate;
a diffusion layer disposed on the silicon layer;
a semiconductor layer that is crystallized using a metal catalyst, disposed on the diffusion layer;
a gate electrode disposed on the substrate, facing a channel region of the semiconductor layer;
a gate insulating layer disposed between the gate electrode and the semiconductor layer; and
source and drain electrodes electrically connected to source and drain regions of the semiconductor layer, respectively.
2 . The thin film transistor according to claim 1 , wherein the silicon layer and the semiconductor layer are formed of polysilicon.
3 . The thin film transistor according to claim 1 , wherein the silicon layer and the semiconductor layer have different grain sizes.
4 . The thin film transistor according to claim 1 , wherein the silicon layer, the semiconductor layer, and the diffusion layer comprise a metal catalyst.
5 . The thin film transistor according to claim 4 , wherein the metal catalyst is formed of one selected from the group consisting of Ni, Pd, Ag, Au, Al, Sn, Sb, Cu, Ti, and Cd.
6 . The thin film transistor according to claim 1 , further comprising an interlayer insulating layer is disposed directly on the gate electrode, wherein:
the silicon layer disposed directly on the substrate;
the diffusion layer is disposed directly on the silicon layer and a portion of the diffusion layer;
the semiconductor layer is disposed directly on the diffusion layer;
the gate insulating layer is disposed directly on the semiconductor layer;
the gate electrode is disposed directly on the gate insulating layer;
the interlayer insulating layer is disposed directly on a portion of the gate insulating layer; and
the source and drain electrodes are insulated from the gate electrode by the interlayer insulating layer.
7 . The thin film transistor according to claim 1 , wherein:
the gate electrode is disposed directly on the semiconductor layer;
the gate insulating layer is disposed directly on the semiconductor layer and a portion of the diffusion layer;
the silicon layer is disposed directly on the substrate;
the diffusion layer is disposed directly on the silicon layer;
the semiconductor layer is disposed directly on the diffusion layer; and
the source and drain electrodes are connected to the semiconductor layer, via openings formed in the gate insulating layer.
8 . A method of fabricating a thin film transistor, comprising:
forming a silicon layer on a substrate;
forming a diffusion layer on the silicon layer;
forming an amorphous silicon layer on the diffusion layer;
forming a metal catalyst layer on the amorphous silicon layer;
annealing the substrate to convert the amorphous silicon layer into a polysilicon layer;
removing the metal catalyst layer;
patterning the amorphous silicon layer to form a semiconductor layer;
forming a gate insulating layer on the substrate;
forming a gate electrode on the substrate, facing the semiconductor layer;
forming an interlayer insulating layer on the substrate; and
forming source and drain electrodes that are connected to the semiconductor layer.
9 . The method according to claim 8 , wherein the annealing is performed after forming a capping layer between the amorphous silicon layer and the metal catalyst layer.
10 . The method according to claim 8 , wherein the annealing is performed at a temperature of from about 350° C. to about 500° C.
11 . The method according to claim 8 , wherein the metal catalyst layer is formed of one selected from the group consisting of Ni, Pd, Ag, Au, Al, Sn, Sb, Cu, Ti, and Cd.
12 . An organic light emitting diode (OLED) display device comprising:
a substrate;
a silicon layer disposed on the substrate;
a diffusion layer disposed on the silicon layer;
a semiconductor layer that is crystallized using a metal catalyst, disposed on the diffusion layer;
a gate electrode disposed on a channel region of the semiconductor layer;
a gate insulating layer disposed between the gate electrode and the semiconductor layer;
source and drain electrodes electrically connected to the semiconductor layer;
a passivation layer disposed on the substrate; and
a first electrode, an organic layer, and a second electrode disposed on the passivation layer and electrically connected to one of the source and drain electrodes, the organic layer being disposed between the first and second electrodes.
13 . The OLED display device according to claim 12 , wherein the silicon layer and the semiconductor layer are formed of polysilicon.
14 . The OLED display device according to claim 12 , wherein the silicon layer and the semiconductor layer have different grain sizes.
15 . The OLED display device according to claim 12 , wherein the silicon layer, the semiconductor layer, and the diffusion layer comprise a metal catalyst.
16 . The OLED display device according to claim 15 , wherein the metal catalyst is formed of one selected from the group consisting of Ni, Pd, Ag, Au, Al, Sn, Sb, Cu, Ti, and Cd.
17 . The OLED display device according to claim 12 , wherein:
the silicon layer is disposed directly on the substrate;
the diffusion layer is disposed directly on the silicon layer;
the semiconductor layer is disposed directly on the diffusion layer;
the gate insulating layer is disposed directly on the semiconductor layer and a portion of the diffusion layer;
the gate electrode is disposed directly on the gate insulating layer;
an interlayer insulating layer is disposed directly on the gate electrode and a portion of the gate insulating layer; and
the source and drain electrodes are insulated from the gate electrode by the interlayer insulating layer.
18 . The OLED display device according to claim 12 , wherein:
the gate electrode is disposed directly on the gate insulating layer;
the gate insulating layer is disposed directly on semiconductor layer and a portion of the diffusion layer;
the silicon layer is disposed directly on the substrate;
the diffusion layer is disposed directly on the silicon layer;
the semiconductor layer is disposed directly on the diffusion layer; and
the source and drain electrodes are connected to the semiconductor layer, via openings formed in the gate insulating layer.