Subresolution silicon features and methods for forming the same
View Patent ↗Novel etch techniques are provided for shaping silicon features below the photolithographic resolution limits. FinFET devices are defined by recessing oxide and exposing a silicon protrusion to an isotropic etch, at least in the channel region. In one implementation, the protrusion is contoured by a dry isotropic etch having excellent selectivity, using a downstream microwave plasma etch.
1. An integrated circuit, comprising:
an active area mesa surrounded by field isolation material, the mesa including a source region, a drain region and a channel region between the source and drain regions;
a semiconductor fin protruding from the channel region of the mesa and isolated from the source and drain regions, the source and drain regions being substantially planar; and
a gate electrode conforming to the surfaces of the fin in the channel region.
2. The integrated circuit of claim 1 , wherein the fin is recessed relative to the planar source and drain regions.
3. The integrated circuit of claim 2 , wherein portions of the channel region adjacent the fin are recessed relative to both the planar source and drain regions and the fin.
4. The integrated circuit of claim 1 , wherein gate electrode forms part of a word line at least partially recessed within the field isolation material.
5. The integrated circuit of claim 1 , further comprising a second channel region spaced from the channel region by the source region, and a second gate electrode, the second channel region comprising a second fin protruding therefrom and the second gate electrode conforming to surfaces of the second fin.
6. The integrated circuit of claim 5 ,
further comprising a second drain region spaced from the source region by the second channel region;
wherein the source, the channel, the drain and the gate electrode define a first transistor of the semiconductor mesa; and
wherein the source, the second channel, the second drain and the second gate electrode define a second transistor of the semiconductor mesa.
7. The integrated circuit of claim 6 , further comprising a first storage capacitor electrically connected to the drain region, a second storage capacitor electrically connected to the second drain region, and a bit line electrically connected to the source region to define two memory cells over the active area mesa.
8. The integrated circuit of claim 1 , wherein the fin has a width of less than about 300 Å.
9. The integrated circuit of claim 1 , wherein the fin has a width of between about 200 Å and 250 Å.
10. A Fin FET device comprising:
a mesa of semiconductor material on a semiconductor substrate, wherein the mesa comprises a contoured portion, wherein the mesa is surrounded on lateral sides by an isolation material, and wherein the isolation material is recessed relative to the contoured portion;
a gate dielectric conformally covering the contoured portion of the mesa; and
a gate conductor conformally covering the gate dielectric covering the contoured portion of the mesa,
wherein the source and drain regions are substantially planar, and the contoured portion is recessed relative to the planar source and drain regions.
11. The device of claim 10 , wherein the mesa of semiconductor material further includes a source region, a drain region and a channel region between the source and drain regions, and the contoured portion protrudes from the channel region of the mesa.
12. The device of claim 10 , wherein portions of the channel region adjacent the contoured portion are recessed relative to the source region, the drain region and the contoured portion.
13. The device of claim 10 , wherein the gate conductor forms part of a word line at least partially recessed within the isolation material.
14. The device of claim 11 , further comprising:
a second channel region spaced from the channel region by the source region, the second channel region comprising a second contoured portion protruding therefrom;
a second drain region spaced from the source region by the second channel region;
a second gate dielectric conformally covering the second contoured portion; and
a second gate conductor conformally covering the second gate dielectric;
wherein the source, the channel, the drain and the gate conductor define a first transistor of the semiconductor mesa; and
wherein the source, the second channel, the second drain and the second gate conductor define a second transistor of the semiconductor mesa.
15. The device of claim 14 , further comprising a first storage capacitor electrically connected to the drain region, a second storage capacitor electrically connected to the second drain region, and a bit line electrically connected to the source region to define two memory cells.
16. A semiconductor structure comprising:
a semiconductor mesa surrounded by field isolation regions, wherein the semiconductor mesa comprises a rounded portion; and
a gate dielectric conformally covering the rounded portion of the semiconductor mesa, wherein the semiconductor mesa further includes a source region and a drain region, and the rounded portion is recessed relative to the source and drain regions.
17. The semiconductor structure of claim 16 , further comprising a transistor gate conductor conformally covering the gate dielectric covering the rounded portion of the semiconductor mesa.
18. The semiconductor structure of claim 17 , wherein the semiconductor mesa further includes a channel region between the source and drain regions, and the rounded portion protrudes from the channel region of the mesa.
19. The semiconductor structure of claim 16 , wherein the rounded portion has a width of less than about 300 Å.
20. The semiconductor structure of claim 16 , wherein the source region and the drain region are substantially planar.