Composite Underfill and Semiconductor Package
Embodiments of the invention exploit physical properties of nanostructures by using nanostructures in a composite underfill. An embodiment is a composite underfill comprising an epoxy matrix applied between a substrate and a semiconductor chip and a suspension of nanostructures distributed within the epoxy matrix. Another embodiment is a semiconductor package comprising a semiconductor chip, a carrier, wherein the semiconductor chip is bonded to the carrier, and a composite underfill comprising a plurality of nanostructures dispersed in an epoxy medium between the carrier and the semiconductor chip. Further embodiments include a method for creating a semiconductor package comprising a composite underfill.
1 . A composite underfill comprising:
an epoxy matrix applied between a substrate and a semiconductor chip; and
a suspension of nanostructures distributed within the epoxy matrix.
2 . The composite underfill in claim 1 , wherein the nanostructures are between 0.5 percent of the composite underfill by weight and 10 percent of the composite underfill by weight.
3 . The composite underfill of claim 2 , wherein the nanostructures are 0.5 percent of the composite underfill by weight.
4 . The composite underfill of claim 1 , wherein the nanostructures comprise carbon, carbon nitride, silicon carbon nitride, tungsten, or silver.
5 . The composite underfill of claim 1 , wherein the nanostructures comprise multi-wall nanotubes.
6 . A semiconductor package comprising:
a semiconductor die;
a substrate, wherein the semiconductor die is electrically coupled to the substrate by solder bumps; and
a composite underfill comprising nanostructures dispersed in an epoxy, wherein the composite underfill is between the semiconductor die and the substrate and around the solder bumps.
7 . The semiconductor package of claim 6 , wherein the nanostructures comprise carbon, carbon nitride, silicon carbon nitride, tungsten, or silver.
8 . The semiconductor package of claim 6 , wherein the nanostructures comprise multi-wall nanotubes.
9 . The semiconductor package of claim 6 , wherein a ratio of the nanostructures to the epoxy is between 1:199 and 1:9 by weight.
10 . The semiconductor package of claim 9 , wherein the ratio of nanostructures to the epoxy is 1:199 by weight.
11 . A semiconductor package comprising:
a semiconductor chip;
a carrier, wherein the semiconductor chip is bonded to the carrier; and
a composite underfill comprising a plurality of nanostructures dispersed in an epoxy medium between the carrier and the semiconductor chip.
12 . The semiconductor package of claim 11 , wherein the plurality of nanostructures is between 0.5 percent and 10 percent by weight of the composite underfill.
13 . The semiconductor package of claim 12 , wherein the plurality of nanostructures is 0.5 percent by weight of the composite underfill.
14 . The semiconductor package of claim 11 , wherein the plurality of nanostructures is a plurality of multi-wall nanotubes.
15 . A method for creating a semiconductor package comprising:
creating solder bumps on a semiconductor chip;
bonding the bumps to a carrier;
applying a composite underfill comprising nanostructures; and
curing the composite underfill.
16 . The method of claim 15 , wherein the composite underfill comprises nanostructures that are between 0.5 percent and 10 percent by weight of the composite underfill.
17 . The method of claim 16 , wherein the composite underfill comprises nanostructures that are 0.5 percent of the composite underfill.
18 . The method of claim 15 , wherein applying the composite underfill comprises applying the composite underfill directly to the carrier before bonding the bumps to the carrier.
19 . The method of claim 15 , wherein applying the composite underfill comprises applying the composite underfill between the semiconductor chip and the carrier and around the bumps after bonding the bumps to the carrier.
20 . The method of claim 15 , wherein curing the composite underfill comprises heating the composite underfill to a temperature between 75° C. and 200° C.
21 . The method of claim 15 , wherein the semiconductor chip includes a flip chip.