Semiconductor device and method for manufacturing the same
View Patent ↗A type semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a plurality of gate electrodes which are formed in gate trenches via gate insulating films, the gate trenches being formed through the second semiconductor layer and the third semiconductor layer; a plurality of impurity regions of the second conductivity type which are formed at regions below bottoms of contact trenches, the contact trenches being formed at the third semiconductor layer in a thickness direction thereof between corresponding ones of the gate trenches and longitudinal cross sections of the contact trenches being shaped in ellipse, respectively; first electrodes which are formed so as to embed the contact trenches and contacted with the impurity regions, respectively; and a second electrode formed on a rear surface of the semiconductor substrate.
1. A method for manufacturing a trench gate type semiconductor device with trench contact structure, comprising:
forming a first semiconductor layer of a first conductivity type above a main surface of a semiconductor substrate;
forming a second semiconductor layer of a second conductivity type on said first semiconductor layer;
forming a third semiconductor layer of said first conductivity type on said second semiconductor layer;
conducting etching treatment for said first semiconductor layer, said second semiconductor layer and said third semiconductor layer via a first mask to form a plurality of gate trenches so as to run into said first semiconductor layer through said second semiconductor layer and said third semiconductor layer;
forming gate electrodes in said gate trenches via gate insulating films, respectively;
conducting isotropic etching for said third semiconductor layer via a second mask to form contact trenches with respective longitudinal semielliptical cross sections at said third semiconductor layer in a thickness direction thereof between corresponding ones of said gate trenches;
conducting ion implantation of impurity of said second conductivity type for bottoms of said contact trenches to form a plurality of impurity regions of said second conductivity type at regions below said bottoms of said contact trenches;
forming first electrodes so as to embed said contact trenches and contacted with said impurity regions, respectively; and
forming a second electrode on a rear surface of said semiconductor substrate.
2. The manufacturing method as set forth in claim 1 ,
wherein said ion implantation is conducted via said second mask.
3. The manufacturing method as set forth in claim 2 ,
wherein said second mask is patterned so that openings of said second mask are orthogonal to said gate trenches, respectively.
4. The manufacturing method as set forth in claim 2 ,
wherein said second mask is shaped in pent roof so that edges of said second mask exposing to openings thereof are protruded inside said contact trenches from edges thereof.
5. The manufacturing method as set forth in claim 2 ,
wherein each of said contact trenches is formed larger than a corresponding one of said openings of said second mask.
6. The manufacturing method as set forth in claim 1 ,
wherein said isotropic etching is chemical dry etching (CDE).
7. The manufacturing method as set forth in claim 1 ,
wherein said etching treatment is anisotropic etching treatment.
8. The manufacturing method as set forth in claim 1 ,
wherein said impurity regions are formed so as to run into said second semiconductor layer from said third semiconductor layer.
9. The manufacturing method as set forth in claim 1 ,
further comprising forming a plurality of interlayer insulating films on said gate electrodes, respectively after said gate electrodes are formed and before said contact trenches are formed.
10. The manufacturing method as set forth in claim 9 ,
wherein said interlayer insulating films function as etching stoppers, respectively for said isotropic etching by forming said interlayer insulating films so that top surfaces of said interlayer insulating films are positioned above said bottoms of said contact trenches, respectively.
11. The manufacturing method as set forth in claim 1 ,
wherein said first semiconductor layer functions as a drain layer, said second semiconductor layer functions as a base layer, said third semiconductor layer functions as a source layer, said first electrodes function as respective source electrodes and said second electrode functions as a drain electrode, so that said semiconductor device functions as a vertical field effect transistor.