IP Library Granted Patent US 9,018,109
Granted Patent B2
US 9,018,109 · App. 12/715,629 · Granted Apr 28, 2015

Thin film transistor including silicon nitride layer and manufacturing method thereof

Inventors: Hidekazu Miyairi (Kanagawa, JP); Erika Kato (Kanagawa, JP); Kunihiko Suzuki (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/4908H01L29/66765H01L29/78669H01L29/78678H01L29/78696H01L27/1214
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Quick Facts
Patent No.
US 9,018,109
App. No.
12/715,629
Granted
Apr 28, 2015
Kind
B2
Abstract

A thin film transistor in which deterioration at initial operation is not likely to be caused and a manufacturing method thereof. A transistor which includes a gate insulating layer at least whose uppermost surface is a silicon nitride layer, a semiconductor layer over the gate insulating layer, and a buffer layer over the semiconductor layer and in which the concentration of nitrogen in the vicinity of an interface between the semiconductor layer and the gate insulating layer, which is in the semiconductor layer is lower than that of the buffer layer and other parts of the semiconductor layer. Such a thin film transistor can be manufactured by exposing the gate insulating layer to an air atmosphere and performing plasma treatment on the gate insulating layer before the semiconductor layer is formed.

Claims (30)

1. A method for manufacturing a thin film transistor comprising:

forming a silicon nitride layer;

exposing the silicon nitride layer to an air atmosphere;

performing plasma treatment on the silicon nitride layer by using argon gas plasma; and

after performing the plasma treatment, forming a semiconductor layer including crystal grains over the silicon nitride layer,

wherein the silicon nitride layer is formed in a first chamber of a multi-chamber,

wherein the semiconductor layer is formed in a second chamber of the multi-chamber, and

wherein the first chamber and the second chamber can be connected with each other in a vacuum state.

2. The method for manufacturing a thin film transistor according to claim 1 , wherein the silicon nitride layer is a gate insulating layer.

3. The method for manufacturing a thin film transistor according to claim 1 , wherein the thin film transistor is incorporated into one selected from the group consisting of an electronic book device, a digital photo frame, a television set, and a cellular phone.

4. The method for manufacturing a thin film transistor according to claim 1 , wherein the silicon nitride layer is exposed to the air atmosphere for two seconds or more and ten minutes or less.

5. The method for manufacturing a thin film transistor according to claim 1 , wherein the silicon nitride layer is formed by a CVD method.

6. The method for manufacturing a thin film transistor according to claim 1 , wherein the silicon nitride layer is formed by a sputtering method.

7. The method for manufacturing a thin film transistor according to claim 1 , wherein the silicon nitride layer is formed by a plasma CVD method.

8. The method for manufacturing a thin film transistor according to claim 1 , wherein the silicon nitride layer is formed by a plasma CVD method using a frequency of 1 GHz or higher.

9. A thin film transistor comprising:

a gate insulating layer at least an uppermost surface of which is a silicon nitride layer;

a semiconductor layer including crystal grains provided over the gate insulating layer; and

a buffer layer over the semiconductor layer,

wherein a concentration of nitrogen of a part of the semiconductor layer is lower than a concentration of nitrogen of the buffer layer,

wherein the part of the semiconductor layer exists in a vicinity of an interface between the semiconductor layer and the gate insulating layer,

wherein the concentration of nitrogen of the part of the semiconductor layer is lower than a concentration of nitrogen of another part of the semiconductor layer.

10. The thin film transistor according to claim 9 , wherein the part of the semiconductor layer exists in a region located at a height of 5 nm or more and 50 nm or less from the interface.

11. The thin film transistor according to claim 9 , wherein the concentration of nitrogen of the part of the semiconductor layer is lower than 1×10 19 /cm 3 .

12. The thin film transistor according to claim 9 , wherein the thin film transistor is incorporated into one selected from the group consisting of an electronic book device, a digital photo frame, a television set, and a cellular phone.

13. The thin film transistor according to claim 9 , wherein the buffer layer comprises another semiconductor layer.

14. The thin film transistor according to claim 13 , wherein the another semiconductor layer includes an NH group.

15. The thin film transistor according to claim 13 , wherein the another semiconductor layer includes an NH 2 group.

16. The thin film transistor according to claim 13 , further comprising a source region provided over the another semiconductor layer.

17. The thin film transistor according to claim 13 , further comprising a drain region provided over the another semiconductor layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2010
From: MIYAIRI, HIDEKAZU; KATO, ERIKA; SUZUKI, KUNIHIKO
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 024015/0146 →
Priority Claims (1)
JP 2009-055878 · Mar 10, 2009 · national
Continuity (1)
Related Publication 20100230677A1 · Sep 16, 2010